Lithography gets the headlines, and I have written about it separately, but a wafer does not become a chip through lithography alone. Lithography decides where a pattern goes. Everything that happens once the pattern exists, the films laid down and the material carved away, is done by deposition and plasma etch tools. These are the machines that consume most of a fab's process steps, and they are where some of the hardest physics in the industry now sits, from atom-thick coatings around suspended nanosheets to holes bored through memory stacks hundreds of layers deep.
In this piece I want to explain how the four main deposition technologies divide the work, why atomic layer deposition (ALD) became the default for gate-all-around transistors, how anisotropic etch actually cuts a straight wall, and why the 3D NAND memory hole is the most punishing etch problem in front-end manufacturing. I take the figures from the book's front-end chapter, and where its sources disagree I keep the range instead of picking a number.
A loop, repeated until the chip exists
A modern 300 mm wafer accumulates a chip through repetition at industrial scale. The book's two source syntheses agree on the order of magnitude but not the exact count. One puts a leading-edge sub-3 nm device at 1,000 to 1,500 sequential process steps, tightened elsewhere in the same document to 1,200 to 1,500. The other says 1,200 to 1,600. Read together they cluster around a 1,200 to 1,500 step core with a wider outer bound of 1,000 to 1,600. Both agree on a fab cycle time of 12 to 16 weeks and on 60 to 90 photolithography mask layers, of which 20 to 28 are exposed on EUV scanners at the 3 nm node.
Every layer is built through the same loop. Deposit a film, pattern it, etch the pattern into the film, and where the resulting surface would otherwise compound into an unmanageable topography, planarize it flat again. What changes from layer to layer is the specific chemistry, not the shape of the loop.
Cycle time is measured in weeks even though no single step takes more than a few hours. What stretches a wafer's journey is repetition: the same wafer routed through hundreds of stations, each with its own queue, hundreds of times over.
The book organises the flow into three stages. Front-end-of-line covers the transistor itself, including nanosheet channel epitaxy, dummy gate patterning and spacers, in-situ doped source and drain growth, and gate-last replacement metal gate with a high-k hafnium oxide dielectric. Middle-of-line covers contact silicidation and tungsten or cobalt plugs. Back-end-of-line builds the copper interconnect, typically twelve to fifteen metal layers, with porous low-k dielectrics, and on the most advanced nodes a backside power delivery network. Deposition and etch appear in all three.
Four ways to lay down a film
Thin-film deposition places layers ranging from atoms to nanometres of conductors (copper, tungsten, cobalt, ruthenium), dielectrics (silicon dioxide, silicon nitride, hafnium oxide) and semiconductors (epitaxial silicon and silicon-germanium) onto the wafer. Four technologies divide the work, and the choice at any layer comes down to two questions. How precisely must the thickness be controlled? And how well must the film coat a three-dimensional shape instead of a flat surface?
| Technology | Mechanism | Thickness control | Step coverage | Typical use |
|---|---|---|---|---|
| PECVD | Gas-phase reaction under RF plasma, 300 to 400°C | +/- 1.0 nm across 300 mm | 75% to 85% | Inter-layer dielectric; SiO2 and SiN cap layers |
| ALD | Self-limiting sequential gas pulses, 150 to 350°C | about +/- 0.05 nm | 100% conformal | High-k gate dielectric (HfO2); TiN liners |
| PVD | Argon plasma sputtering of a target, DC/RF magnetron | +/- 2.0 nm | Line-of-sight only | Copper seed layer; Ta/TaN diffusion barrier |
| Epitaxy | Thermal gas-phase reaction extending the crystal lattice, 600 to 800°C | Single-crystal atomic precision | Set by crystal orientation | SiGe source/drain strain; Si/SiGe channel superlattice |
The distinction between ALD and the other techniques is the one that has driven the most structural change. PECVD and PVD are, in different ways, line-of-sight or gas-flux-dependent processes. They coat exposed surfaces reasonably well but struggle to deposit a uniform film inside a deep, narrow trench or around a stacked structure. PVD is explicitly directional, which suits a copper seed layer on a fairly open via but not the underside of an overhanging feature.
ALD replaces continuous gas flow with a pulse-and-purge cycle. Each precursor pulse reacts with the wafer surface until every available reaction site is used up and no more, which is what makes the process self-limiting. The result is essentially 100 percent conformal coverage, the same thickness on a flat top, a vertical sidewall and the underside of a re-entrant feature. That property is what a gate-all-around nanosheet transistor requires. Depositing a hafnium oxide gate dielectric and a titanium nitride work-function metal evenly around a horizontal channel suspended on all sides is not possible with a directional technique. That is why ALD, rather than PECVD or PVD, is now the default for the replacement-metal-gate stack at leading-edge nodes. I would summarise the trade as thickness precision and coverage against speed: ALD is slow because it builds one atomic layer per cycle, but at these dimensions nothing else reaches the surface.
Epitaxy: growing crystal, not laying film
Epitaxy is a different category. Instead of depositing an amorphous or polycrystalline film, it extends the wafer's existing single-crystal lattice, atom by atom, into a new layer that shares its orientation. That lets source and drain regions be grown as in-situ doped, strained crystal, rather than formed by damaging the lattice and repairing it afterward. Phosphorus-doped silicon (SiP) is grown for NMOS and boron-doped silicon-germanium (SiGe:B) for PMOS. The lattice mismatch between silicon and silicon-germanium puts the crystal under mechanical strain, which measurably improves carrier mobility.
The same technique, used earlier in the flow, grows the alternating silicon and silicon-germanium superlattice from which gate-all-around nanosheets are patterned in the first place. This is a point I think gets missed: at leading-edge nodes epitaxy is doing three jobs at once. It builds the channel stack, it sets dopant concentration in the source and drain, and it supplies the strain, all in the same family of process steps.
Etch: chemistry for selectivity, ions for direction
Where deposition adds material, plasma etch removes it selectively, cutting the contact vias, shallow trenches and channel geometries that lithography has only drawn in photoresist. Anisotropic reactive-ion etching combines two mechanisms in the same reactor, and the balance between them decides whether the sidewalls come out near-vertical.
The first mechanism is chemical. Fluorocarbon gases such as CF4, C4F8 and CHF3 are broken apart by a 13.56 MHz RF field into reactive radicals, chiefly atomic fluorine. Fluorine reacts with exposed silicon to form volatile silicon tetrafluoride, which the pumps carry away. Chemistry alone, however, is isotropic. It attacks in every direction, undercuts the mask and rounds the profile.
The second mechanism corrects that. A DC self-bias accelerates heavy argon ions straight down, perpendicular to the wafer, sputtering material at the bottom of a trench far more aggressively than at its sidewalls. Chemistry gives selectivity and removal rate. Directional bombardment gives verticality. Together they yield sidewall angles above 89.5 degrees from horizontal.
A refinement, atomic layer etching, makes this self-limiting. A gas-adsorption step, for example chlorine, chemically modifies only the top atomic layer of exposed silicon. A low-energy argon-ion step then removes only that modified layer without damaging the crystal below. Depth control reaches about 0.1 nm per cycle. The price is throughput, which is significantly lower than continuous reactive-ion etching. So the same trade appears here as in deposition: the finer the control, the slower the tool, and the process engineer chooses the layers where that control earns its cost.
The high-aspect-ratio frontier: 3D NAND memory holes
The book puts it well in one line: a trench that is merely deep is easy, and a trench that is deep, narrow, perfectly vertical and does not twist, bow or clog on the way down is the hardest single problem in front-end etch. The memory hole in 3D NAND poses exactly that problem at scale.
Modern 3D NAND alternates more than 232 layers of oxide and nitride, an "ONON" stack, to form the vertical channel structure. Etching a memory hole through the entire stack in a single continuous pass means holding an aspect ratio, depth divided by width, above 80 to 1. At that ratio standard room-temperature plasma chemistry fails in three characteristic ways.
| Failure mode | Mechanism | Primary mitigation |
|---|---|---|
| Profile bowing | Reactive species deplete before reaching the bottom, widening the mid-profile | Cryogenic cooling to about minus 60°C slows lateral chemical attack |
| Twisting | The etch front loses directional control as depth-to-width passes 80:1 | SF6 / O2 / Ar cryogenic chemistry; tighter ion directionality |
| Clogging | Byproducts redeposit in the narrow channel faster than they can be pumped out | Cryogenic process with tuned gas flow and pump-out cycling |
Reactive species and etch byproducts struggle to reach or leave the bottom of the hole. The hole widens partway down and narrows again, which is bowing. The etch front drifts off-axis as it descends, which is twisting. Redeposited byproducts block the channel, which is clogging.
The industry's main countermeasure is cryogenic etching. The wafer is cooled to approximately minus 60°C during the etch, using an SF6, oxygen and argon plasma. The low temperature slows the chemical reaction enough to suppress lateral attack on the sidewalls, while ion bombardment keeps driving the front straight down. As vendors push layer counts well past 300 in their next nodes, the aspect-ratio and thermal-budget demands on this one step keep tightening. The book calls it one of the more capital- and process-intensive single operations in the whole memory flow, and I see no reason to disagree.
Doping and planarization keep the loop workable
Two other operations sit inside the loop and deserve a short mention. Transistor conductivity is set by doping. The book documents one route in depth, the in-situ doped epitaxial source and drain described above, which sets dopant concentration and strain in a single step and has become standard at leading-edge GAA nodes. Conventional ion implantation, followed by a rapid anneal to activate dopants and repair damage, remains part of the flow for wells and channels, but the book does not give node-specific implant energies or doses, and I will not supply them.
Chemical mechanical planarization, CMP, is what makes repeated multilayer processing tractable. Without it the topography of one patterned layer would compound into the next, and a via etched into an uneven surface would produce uneven focus on the layer above. CMP combines a chemically reactive slurry with mechanical pad pressure to return the wafer to a globally flat surface after essentially every metallization and dielectric layer. Interlayer planarization is typically specified to below 0.1 nm RMS roughness. The removal rate follows Preston's Law, MRR = Kp x P x V, where Kp is a slurry and pad coefficient, P is downward pressure and V is the relative velocity of wafer and pad. In practice engineers tune pressure and platen speed for a given slurry instead of changing chemistry layer to layer.
CMP is also load-bearing in copper dual-damascene, where etched trenches are filled by electroplated copper and CMP removes the excess overburden, and in backside power delivery. To move the power grid to the back of the wafer, the substrate is thinned from about 775 microns to under 500 nanometres by CMP, before nano-scale through-silicon vias are etched to reach the transistor terminals. The book reports that this cuts interconnect IR voltage drop by more than 30 percent and frees 15 to 20 percent of frontside routing area. The same theme returns in advanced packaging, where hybrid bonding depends on the same class of sub-nanometre flatness.
How the loop is checked, and why yield is so sensitive to it
Each pass through deposit, etch and planarize has to be measured before the next begins, because an unmeasured error compounds forward. The book names four inline tools. Broadband optical inspection, such as KLA's 39xx series, scans the whole wafer for particles down to roughly 10 nm. Critical-dimension scanning electron microscopy resolves about 0.5 nm and verifies that etched line widths match the target. Transmission electron microscopy at 200 kV gives near-atomic cross-sections, destructive and slow, but the only way to confirm that a copper via filled completely. X-ray photoelectron spectroscopy checks surface composition, for example that an ALD hafnium oxide film has the right oxygen-to-hafnium ratio and not just the right thickness.
| Defect | Origin | Detection and effect |
|---|---|---|
| Killer particle | Dust above about 20 nm during exposure | Dark-field inspection; shorts adjacent lines, zero yield on that die |
| Pattern bridging | Incomplete resist exposure or scumming | CD-SEM; line-to-line short |
| Line edge roughness | Statistical fluctuation of photo-acid in EUV resist | CD-SEM; raises off-state leakage |
| Copper via void | Incomplete electroplating in a high-aspect via | TEM cross-section; open circuit |
These defects roll up into one economic number, die yield. The book uses Murphy's model, in which yield falls off non-linearly as defect density times die area grows. Every particle, bridge, roughness excursion and via void feeds into that defect density. Because the curve is non-linear, small improvements in process-induced defects produce disproportionate gains in sellable die per wafer. That is the real reason deposition and etch discipline is not a technical nicety.
What scale looks like
The same process has to run continuously, not once on a champion wafer. TSMC's Gigafabs are the clearest public example. The book reports more than 100,000 wafer starts per month per Gigafab, against roughly 25,000 to 40,000 for a standard fab, ISO Class 1 cleanrooms, fully automated overhead hoist delivery of wafer carriers in under 60 seconds, and about 50,000 tons per day of ultra-pure water at roughly 65 percent recycling. TSMC's target of 85 percent recycling by 2028 is a corporate goal, not a current fact. The book reports N3B and N3E yields above 80 percent and a global foundry revenue share above 61 percent in the first quarter of 2024. It also notes it could not substantiate a daily carrier-movement count, and I leave that out.
What I take away
First, the choice among PECVD, ALD, PVD and epitaxy is a choice between precision, conformality and speed. ALD's atomic control and full conformality are what make gate-all-around transistors buildable at all, and the cost is throughput.
Second, etch is a balance of two mechanisms, chemical selectivity and directional ion bombardment. Nearly every advance in etch is a way of tilting that balance, as atomic layer etching does for control and cryogenic cooling does for depth.
Third, the memory hole is where the balance is most tested. An aspect ratio above 80 to 1 through 232-plus layers, with counts heading past 300, makes one etch step among the most demanding in the whole flow, and it will keep tightening.
Fourth, none of this is visible in the headline node name. A wafer's 1,200 or so steps, its 12 to 16 weeks in the fab and its yield all depend on these unglamorous tools, made by a small group of equipment vendors, which is why access to deposition and etch equipment sits alongside lithography in export-control thinking.