Every populated circuit board, whether a smartphone mainboard, an EV traction inverter or a life-support monitor, goes through the same four-stage gauntlet: paste, place, reflow, inspect. Most discussion of electronics manufacturing focuses on the chips. I want to look at the line that joins them to the board, because what actually holds a component in place for the life of a product is a few micrograms of metal alloy and a thermal profile. Get the material chemistry or the profile wrong and no placement machine can rescue the board.

This article follows a board through the line in the order it travels: solder paste and stencil printing, paste inspection, placement, reflow, through-hole joining, and inspection, and then looks at what the yield and throughput numbers really mean. Figures come from the book's chapter on SMT and THT assembly. Where the book uses an illustrative assumption instead of a published statistic, I will say so.


Six stages, one architecture

A populated board, a PCB or PCBA in industry usage, moves through a strictly sequential inline process. A bare board is loaded automatically, and in many modern lines laser-marked with a two-dimensional DataMatrix barcode for lot and unit traceability before a single component is placed. From there it passes through the same architecture whether the line is in Chennai or Stuttgart: stencil printing, inline solder paste inspection, pick-and-place, reflow soldering, and automated optical and X-ray inspection. Each stage solves a problem the previous one cannot. Printing deposits the metal that becomes the joint. Inspection catches printing defects before a component buries them. Placement positions the part to micron-level accuracy. Reflow converts paste and lead into one metallurgical bond. Final inspection catches whatever slipped through.

The SMT line, in the order a board travels it
Materials-critical stages are shaded amber: paste deposition and the reflow profile decide joint quality.
Print SAC305 paste > SPI 3D paste check > Place Chip + precision > Reflow Nitrogen oven > AOI 3D optical > AXI X-ray THT: wave or selective soldering For connectors, transformers, high-current parts

Solder paste: the metal that becomes the joint

Printing comes first. A laser-cut or electroformed nickel stencil, roughly 100 micrometres thick as a common working point, sits over the copper pads. A squeegee under closed-loop pressure, reported at 0.18 to 0.25 kilograms per centimetre, drags solder paste across it and deposits it through the apertures onto each pad.

In the overwhelming majority of modern lead-free lines the paste is SAC305, an alloy of 96.5% tin, 3.0% silver and 0.5% copper. It was chosen because it removes the lead that dominated electronics soldering before RoHS-era regulation, while still reflowing at a temperature the rest of the board can tolerate. This is the one material choice in the line that touches every joint on every board, so it is worth understanding what the alloy does. Tin is the bulk of the joint and the metal that bonds to copper. Silver and copper adjust the melting behaviour and the strength of the finished joint. The alloy melts, or reaches liquidus, at roughly 217 to 220°C. That number anchors everything in the reflow profile below.

Print quality sets a ceiling on everything downstream. A bridged or starved deposit cannot be fixed by a more careful placement head or a better reflow profile. It has to be caught, or it becomes a solder defect that survives to the end of the line.

Catching it is the job of solder paste inspection (SPI). Inline 3D SPI, built on dual-projection Moiré interferometry from vendors such as Koh Young and CyberOptics, measures effectively every paste deposit on every board, not a sample: volume, height and area. Deposit height is typically reported at 80 to 120 micrometres, with a tolerance around plus or minus 20% of stencil thickness, and printers are commonly held to a paste-height repeatability of Cpk above 2.0, well above the 1.33 often treated as a general manufacturing minimum. The economics are simple. A board rejected at SPI costs a re-run of one step. The same defect found after reflow means desoldering and reworking a fully populated board.

Process stepBenchmark parameterWhy it matters
Paste alloySAC305 (96.5 Sn / 3.0 Ag / 0.5 Cu)Lead-free standard for RoHS-compliant reflow
StencilLaser-cut or electroformed nickel, ~100 µmSets deposit geometry and repeatability
Squeegee pressure0.18 to 0.25 kg/cm, closed loopGoverns paste transfer consistency
SPI technologyDual-projection 3D MoiréChecks effectively 100% of deposits
SPI height / tolerance80 to 120 µm; about plus or minus 20% of stencil thicknessFlags bridging and insufficient paste
RepeatabilityCpk above 2.0Well above general minimums

Placement: speed figures that are not what they seem

Placement is where the line earns its reputation as one of the most capital-intensive automated processes in electronics. Two head architectures dominate. Rotary heads, sometimes called chip shooters, pick continuously from tape feeders and align optically on the fly. They trade force and flexibility for raw speed and are the workhorse for tiny passives (0201, 01005 and increasingly 008004-scale parts) that make up most of a board's component count but a small share of its value. Gantry-style multi-nozzle heads move more deliberately but carry vision systems that verify fine-pitch BGA geometry, lead pitch down to 0.3 millimetres and odd-form connectors. A line typically combines both.

The metric is components per hour (CPH), and it is easy to misread. Line-level figures for high-volume mobile assembly run from 80,000 to over 150,000 CPH, a combined figure from several modules in sequence. ASM's SIPLACE TX series is specified at up to 96,000 CPH per module at plus or minus 25 micrometres, 3-sigma, which the vendor contrasts with a standard-placement benchmark of 30,000 to 45,000 CPH at plus or minus 35 micrometres. These are not competing claims about one machine. One is a single head's ideal maximum, the other a whole line's combined output. The book calls treating them as comparable, or assuming a line runs at the sum of its modules' rated speeds under a real component mix, the single most common way a line-sizing exercise overstates its own throughput.

The book gives an illustration, using an assumed 800 placements per board that is explicitly not a published average. At the midpoint of a standard-class range, around 37,500 CPH, that board takes about 77 seconds, or roughly 47 boards an hour. A 96,000 CPH module takes about 30 seconds, roughly 120 boards an hour, about 2.5 times the throughput. The point stands even if the assumed board size changes: placement-head selection is among the largest capital decisions in sizing a line, ahead of the oven or inspection stations.

Illustrative boards per hour for one 800-placement board
Assumption for arithmetic only: 800 placements per board. The book states this is not a published industry average. Placement stage in isolation.
Standard-class (~37,500 CPH) ~47 boards/hr SIPLACE TX-class (96,000 CPH) ~120/hr Roughly 2.5 times faster. The oven can still cap the line below either figure.

Global placement supply is a short list: Fuji Corporation and Panasonic Factory Solutions in Japan, ASM Assembly Systems under Singapore-headquartered ASM Pacific Technology (SIPLACE, Germany-engineered), Yamaha Motor in Japan and Hanwha Precision Machinery in South Korea. Independent market research puts ASM PT's share of the high-end placement market at roughly 22%, a leading but not dominant position and notably below the 35%-plus figure sometimes assumed. The same names recur at Foxconn, Pegatron, Jabil, Dixon Technologies and Syrma SGS.


Reflow: the profile is the process

Placement positions a part but does not bond it. The bond forms in forced-convection reflow, where the board travels through a tunnel oven with independently controlled zones, reported at 8 up to 15 top-and-bottom zones, under nitrogen. The thermal profile has four physically distinct phases, and this is where the paste chemistry meets thermodynamics.

Preheat raises the board from ambient toward roughly 150 to 180°C at a ramp of 1.0 to 3.0°C per second. Ramping faster risks thermal shock, including cracking in ceramic capacitors, before the paste has even started to melt.

Soak holds 150 to 200°C for roughly 60 to 120 seconds. It serves a chemical purpose more than a thermal one. It activates the flux in the paste, which cleans oxides off the pads and leads, and it equalises temperature so that heavy parts such as large ICs and connectors reach the peak zone close to the same temperature as small passives.

Reflow is the peak zone, at 240 to 260°C across sources, with most converging on 245 to 255°C for SAC305, comfortably above the alloy's 217 to 220°C liquidus but bounded above by component tolerance. The critical variable is time above liquidus (TAL): the paste must stay molten for roughly 45 to 75 seconds to fully form the copper-tin intermetallic, Cu6Sn5, that gives the joint its mechanical and electrical integrity. Too short leaves a weak bond. Too long risks excessive intermetallic growth and thermal stress on components.

Cooling descends to below 100°C at under roughly 4°C per second, which controls the solder's grain structure and avoids shock.

Schematic SAC305 reflow profile
Shape drawn from the phase parameters above, not measured data. The shaded band is time above liquidus (about 217°C), targeted at 45 to 75 seconds.
Liquidus ~217 to 220°C Preheat to 150 to 180°C Soak 60 to 120 s Reflow peak 245 to 255°C Cooling under ~4°C/s TAL 45 to 75 s
PhaseTemperatureDuration / rampPurpose
PreheatAmbient to ~150 to 180°C1.0 to 3.0°C per secondAvoid shock and ceramic cracking
Soak150 to 200°C60 to 120 sFlux activation; equalise temperature
Reflow240 to 260°C (245 to 255 typical)TAL 45 to 75 s above ~217°CForm Cu6Sn5 intermetallic bond
CoolingTo below 100°CUnder ~4°C per secondControl grain structure

Nitrogen and voids

Nitrogen inerting keeps oxygen low enough to prevent copper and solder oxidation and to improve wetting on fine pads. Reported targets differ by source: below 100 ppm oxygen in general line-architecture references, 20 to 50 ppm for Heller's own 13-to-15-zone ovens. The book reads that as general guidance versus a tighter vendor-specific specification, not a real disagreement about the physics. Delta-T across the board is held under about 2°C in Heller's reference, so every joint reflows in the same narrow window.

For the highest-reliability assemblies, such as automotive power modules, ovens can add an inline vacuum reflow module. Pulling below roughly 10 Torr while the solder is molten reduces BGA and QFN void area from a typical above 15%, the ceiling IPC Class 3 otherwise allows, to about 1% to 3%. The cost is extra oven length and cycle time. It is a direct trade of throughput for joint reliability.

Belt speed sets a throughput ceiling independent of placement. Heller's 2000-series ovens are specified at 1.0 to 1.8 metres per minute. Using an assumed board pitch of about 350 millimetres, again for arithmetic only and not a published figure, 1.4 metres per minute gives about 4 boards per minute, or 240 an hour. If placement is sized to outrun that, the oven, not the placer, is the real bottleneck, however impressive the CPH rating.


Why the through-hole joint never went away

Surface mount displaced through-hole as the dominant high-volume method decades ago but never eliminated it. The industry's own definition of a populated board is a substrate populated with soldered surface-mount and through-hole components. Through-hole technology (THT) inserts leads through plated barrels and solders them either by wave soldering, where the underside passes over a standing wave of molten solder, or by selective soldering on mixed-technology boards, which applies a localised solder wave only to the specific joints that need it and leaves the already-reflowed SMT joints undisturbed.

It persists under the same standards as SMT. IPC-A-610 sets visual acceptance criteria for SMT, through-hole, fillets and placement across all three IPC reliability classes, and J-STD-001 sets the parallel process requirements for solder materials, flux classification and cleanliness. So THT is not a legacy exception. It is a fully specified process running beside SMT on the same floor.

The reason is concentrated at a specific margin. A soldered through-hole barrel forms a fillet that wraps the lead through the full thickness of the board, not one planar pad. That geometry tolerates shock, vibration and thermal cycling better than a similar-footprint SMT joint. A through-hole lead also has a larger cross-section, so it carries more current and dissipates more heat than a comparable SMT pad without derating. Those two properties are what IPC Class 3, the category for high performance and harsh environment electronics, is built around. The book names commercial avionics, military radar, life-support medical systems and EV traction inverters as characteristic examples. Board-edge connectors with repeated mating cycles, power transformers, terminal blocks and discrete high-current power semiconductors are where a hole and a wave of solder still win, even on boards that are otherwise almost entirely SMT.

DimensionSMT jointThrough-hole joint
Joint geometryAnchored to a planar padFillet wraps lead through full board thickness
Mechanical stressMore exposed to shock, vibration, cyclingTolerates them more robustly
Current and heatDerates at comparable package sizeLarger cross-section carries more
Joining methodPaste, then reflowWave or selective soldering
Class 3 inspection anchorVoid and fillet criteriaMinimum 75% vertical barrel fill

That 75% vertical fill is the most concrete quantitative anchor the book has for THT: molten solder must wick up at least three-quarters of the plated hole depth around the lead. A shortfall is frequently invisible from the top of the board, so it is typically verified by X-ray or cross-section. The book notes that wave and selective soldering throughput, a direct cost-per-joint comparison against SMT, and India's installed base of through-hole equipment are not covered by its sources and are marked as evidence required. I will not estimate them either.


Inspection, and the gap between rated and real

The last stage catches what the first five let through. 3D automated optical inspection (AOI), typically built on eight-projector structured-light systems with resolution around 10 micrometres per pixel, inspects fillets from several angles, and is commonly specified with a false-call rate below roughly 500 ppm. That matters because a station that flags too many good boards creates its own rework bottleneck. 3D automated X-ray inspection (AXI) covers what optics cannot see: voids and incomplete joints hidden under a BGA or QFN.

Yield figures across sources measure different things, and conflating them overstates how well a line runs. A placement misplacement rate under 5 DPMO and a placement-station first-pass yield above 99.95% describe pick-and-place in isolation. Line-level first-pass yield, reported above 98% to above 98.5%, is the fraction of boards clearing every inspection point from SPI through AOI and AXI without rework. A 99.95% station and a 98.5% line are not in tension. The line is simply the compounded probability of clearing several stages, so it must be lower than any one of them.

Benchmark targets for a high-volume SMT line
Per SMTA and IPC-A-610 benchmark guidelines, as reported in the book. Different scopes, so not directly comparable.
Placement-station FPY above 99.95% Line-level FPY above 98.5% Line-level OEE above 85% Bars are scaled to the stated percentages. Defect target: under 10 DPMO overall (IPC Class 3).

Getting a line to run near its rated CPH and target yield at once is a separate problem from designing it. That is what overall equipment effectiveness (OEE) captures: availability, run-rate performance and first-pass quality combined. SMTA benchmarks cite a target above 85% for high-volume production. A line well below that is losing output to downtime, running under rated speed or generating rework, and a placement-head data sheet says nothing about any of it.


India: hundreds of lines, imported equipment

India's EMS sector has expanded its SMT line count substantially under the Production Linked Incentive scheme for mobile phones and IT hardware, with major facilities at Foxconn Sriperumbudur, Pegatron Chennai, Dixon Technologies Noida, Syrma SGS, Amber Enterprises and Kaynes Technology now operating what industry references describe as hundreds of SMT lines in aggregate. The equipment, however, is reported at more than 95% imported, from the same vendor list that recurs throughout: Fuji, ASM Siplace, Panasonic, Yamaha and Hanwha for placement, Heller and Rehm for reflow ovens, and Koh Young and CyberOptics for SPI. What has localised is support, not manufacture: distribution, recalibration and spare-parts centres in Noida, Chennai, Bengaluru and Pune, servicing an installed base India does not yet build. The book marks India's exact active line count as of 2026, its domestic SMT equipment production and the share of EMS facilities holding IPC certification as unresolved, pending a dedicated ICEA and MeitY capacity audit.


What to take away

First, the joint is a materials and thermal problem. SAC305 paste, a 217 to 220°C liquidus and 45 to 75 seconds above it to form Cu6Sn5 are what make a joint, and no amount of placement speed compensates for a bad profile.

Second, defects are cheapest at the start. Full inline SPI at a Cpk above 2.0 exists because a paste fault found after reflow means rework on a populated board.

Third, read spec sheets by scope. Module CPH is not line CPH, station yield is not line yield, and the oven belt can cap a line below its placers. Two of the book's own worked figures are assumptions, not statistics, and I have kept them labelled.

Fourth, through-hole survives because of physics, not habit. Mechanical robustness and current capacity at the Class 3 margin have no SMT substitute at comparable size.

Finally, India has scaled the number of lines faster than it has built the equipment behind them, at over 95% imported. What it has built so far is the service layer, and the data needed to size the gap precisely still has to come from an audit that has not been done.