Silicon Carbide: The 150mm to 200mm Substrate Transition

Silicon carbide has a strange cost structure. The device that ends up in an 800V electric vehicle inverter is not expensive mainly because of the transistor design or the fab. It is expensive because of the crystal it is built on. The substrate, grown one atomic layer at a time at temperatures above 2,400°C, is the dominant cost line in a finished SiC part. That is why the industry's most important current project is not a new device architecture. It is moving from 150mm to 200mm wafers.

In this piece I lay out why SiC wins in the first place, why the substrate is the bottleneck, what the 200mm move is worth, and how three companies, Wolfspeed, Infineon and onsemi, have chosen to position themselves around it. I use the figures from the ESDM book and keep its hedges, including where two sources give different numbers for the same thing.

Why silicon carbide, briefly

Every power semiconductor decides how much of the current passing through it becomes useful work and how much becomes heat. For six decades that job was done almost entirely in silicon. Wide-bandgap materials change the arithmetic through a physical property silicon cannot improve on.

A material that resists breakdown at a much higher field can be built with a thinner drift layer for a given voltage rating, and a thinner drift layer means lower on-state resistance and lower conduction loss for the same footprint. SiC also carries roughly three times silicon's thermal conductivity, which lets it run at junction temperatures of 175°C to 200°C where a comparable silicon device would already be derating.

The payoff shows up at the vehicle level. OEM test-bench audits cited in the book attribute a 5% to 7% increase in usable EV range to swapping a silicon IGBT for a SiC MOSFET in the main traction inverter of an 800V platform, purely from lower conversion losses. The same logic extends to DC fast chargers, solar inverters and high-speed rail. The projected 2026 global SiC power device market is $3.5 billion to $5.0 billion, per Yole Group data as summarised in the book.

A device-level comparison

onsemi's technical material gives the clearest single illustration. Its 1,200V EliteSiC M3S MOSFET against a comparable 1,200V silicon IGBT module:

These are onsemi's own specifications, so read them as a manufacturer's best case. The direction of the advantage is not in doubt; the exact percentages depend on the design.

The substrate is the bottleneck

SiC boules are grown by physical vapour transport (PVT) above 2,400°C. The resulting crystal's usable yield is acutely sensitive to defect density, with micropipes and basal-plane dislocations chief among the problems. The book states it plainly: the substrate, not device fabrication, is the dominant cost line in a finished SiC part. The process is slow, energy-intensive and yield-sensitive at every producer, regardless of wafer diameter.

Substrate supply is concentrated in a short list of merchant and captive producers: Wolfspeed and Coherent (formerly II-VI) in the United States, ROHM and SiCrystal in Japan and Germany, STMicroelectronics and Norstel in Sweden, and SK Siltron CSS in South Korea. Gallium nitride avoids this bottleneck largely by not needing it. GaN-on-silicon grows on standard 150mm and 200mm silicon wafers and rides existing CMOS-derived fab lines. That is a large part of why GaN has settled in lower-voltage, cost-sensitive segments and SiC has taken the high-voltage, high-power ones.

Why 200mm, and what it is worth

A 200mm wafer has about 1.8 times the usable surface area of a 150mm wafer. That is just geometry: the area scales with the square of the diameter, and (200/150) squared is about 1.78. The economic argument is that SiC crystal growth cost scales far more slowly than the area it produces. More usable area per boule means the slow, expensive growth process is amortised over more dies.

The book gives two different cost targets, and the gap between them is informative.

• The wide-bandgap technical reference puts the industry-wide target at a 20% to 30% reduction in per-die cost from the 150mm to 200mm move.
• Wolfspeed's own financial presentations target a 50% reduction in per-die manufacturing cost from the larger format alone.

My reading, following the book, is that the difference reflects how the transition is being done. Wolfspeed built its 200mm line from the ground up around the larger diameter. Most of the rest of the industry is requalifying existing fab lines that were not designed for 200mm. Infineon, STMicroelectronics, Wolfspeed, ROHM and onsemi all run SiC lines across both diameters today. One line of the book's summary chapter states the range as 20% to 50%, which is the same two numbers put together rather than a third estimate.

Wolfspeed: the merchant supplier that sells to its competitors

Wolfspeed, formerly Cree, is the leading pure-play maker of SiC substrate wafers and power devices. It is estimated to control 50% to 60% of global merchant SiC substrate supply, including sales to Infineon, STMicroelectronics and onsemi itself. That customer list is the most striking thing about it. Wolfspeed sells the raw material that its own device-level competitors turn into finished power modules, so its fab investment decisions act as a capacity constraint on the industry's wider SiC roadmap, not only on its own product line.

The footprint is split across two sites, and the numbers are large.

Raw silicon and carbon powder run through Siler City, and finished boules move to Mohawk Valley. The combined outlay is roughly $6 billion. Automation is central to the economics: at more than 115,000 square feet of ISO Class 1 cleanroom, full automation is what lets the fab turn a 1.8x wafer-area gain into an 8.4x increase in die output relative to Wolfspeed's legacy 150mm capacity, rather than a smaller gain limited by manual handling. That 8.4x is a company figure, and I would treat it as one.

The strategic reading is that a supplier this concentrated, selling to its own competitors, turns its balance sheet and capacity roadmap into an input the rest of the industry has to plan around. A device maker's decision to integrate vertically does not fully insulate it if the underlying boule still traces back to a small number of merchant crystal-growth facilities.

Infineon: scale across every voltage class

Infineon Technologies of Germany is the industry's largest player by most measures. The book carries two market-share figures for it, and they are not contradictory. Infineon's own positioning claims over 30% of the global power MOSFET and IGBT module category. Omdia's broader power-semiconductor company ranking puts its overall power semiconductor share at roughly 21.0% for the 2023 base year. Both are consistent with Infineon being number one; they answer different questions, because market share is only comparable once the category boundary is specified.

Its portfolio maps across the voltage-class structure of the whole discrete market:

HybridPACK Drive is reported, per automotive OEM audits, to ship inside more than 35% of European and Asian electric vehicles. So Infineon's SiC push is an extension of an incumbent position. A customer can get a silicon MOSFET, a silicon IGBT or a SiC MOSFET under one commercial relationship. The cost is that SiC is a smaller slice of its portfolio than its silicon legacy.

onsemi: the vertically integrated SiC bet

onsemi has built a narrower position around EliteSiC, a product family that spans the whole chain: 150mm and 200mm SiC boules, epitaxial wafers, planar and trench MOSFET dies and finished 1,200V power modules. The logic is control of substrate quality. Owning the crystal means owning the defect density that determines SiC device yield, instead of depending on a merchant supplier. The book lists Tesla and Hyundai automotive traction inverters, solar string inverters and AI server power supply units among its customers, and TrendForce data confirm onsemi held 11.6% of the global SiC power device market in 2023, up on the prior year and a top-three position. Growth into 2024 and 2025 points to a mid-teens share on an extrapolated basis, but that later figure is an estimate, not a confirmed data point.

For a design team the risk profiles differ. Choosing Infineon means one supplier across nearly every voltage class, at the cost of a smaller SiC share. Choosing onsemi means SiC substrate, epitaxy and device fabrication inside one company, which narrows external yield dependencies but comes with a narrower catalogue outside SiC. The book notes that large automotive and industrial customers frequently qualify both in parallel rather than be single-threaded on either strategy. I find that sensible; neither approach is strictly better.

India and the same bottleneck

India's real footprint in wide-bandgap devices is early-stage. Continental Device India Limited (CDIL) runs discrete semiconductor packaging lines in Mohali and is expanding under SPECS to process SiC discretes and power MOSFETs alongside its silicon lines. Domestic SiC substrate manufacturing capacity, and Indian discrete fabrication beyond packaging, are marked in the book as evidence required, pending a MeitY component-level capacity survey.

The lesson from the Wolfspeed story is that the physical bottleneck of the SiC chain sits at the substrate and crystal-growth end, not at device design or module assembly. Any Indian SiC device effort would inherit that dependency, on a supply base located almost entirely outside India. Packaging is a sensible first step, but it is the least constrained layer.

Where the frontier goes next

The book's later chapter on wide and ultra-wide bandgap materials makes one point I think is worth repeating. The 200mm transition is an industry-wide migration, not one company's bet. Every SiC device maker is managing some version of the same requalification exercise on its own timeline, and the aggregate pace of that migration, more than any single fab announcement, will decide how quickly SiC costs converge with silicon at a given voltage class. Gallium oxide is discussed as an eventual complement at extreme voltages, but the book is clear that it is a research-stage material with no documented market, and I will not add numbers it does not have.

Why yield compounds at the substrate

It helps to understand why a crystal defect is so much costlier than a fab defect. A device fab step that goes wrong scraps a wafer's worth of processing. A substrate defect goes into everything built on that wafer. Micropipes and basal-plane dislocations in the boule pass into the epitaxial layer and then into the finished devices, and they set a ceiling on usable yield that no downstream step can lift. This is why onsemi's argument for owning the boule is not a marketing line. Controlling the substrate is the most direct way to control the number that drives cost.

It also explains why the larger wafer matters twice. A 200mm boule gives more usable area for the same slow growth process, so cost per die falls. But the economic gain depends on crystal quality holding at the larger diameter, which is presumably part of why the industry-wide target range is more cautious than Wolfspeed's own. That is my reading, not a statement from the source.

A different GaN story: the same substrate, another use

The SiC substrate has a second life in the book's later chapter on wide-bandgap materials. GaN power devices ride silicon for cost, but RF GaN increasingly rides silicon carbide for performance. GaN-on-SiC trades the cheaper substrate for better lattice matching and higher thermal conductivity, and those matter more than cost per watt in a 5G base-station power amplifier or a defense radar module that has to shed heat from a dense antenna array. The book does not specify wafer diameters for GaN-on-SiC and marks it as evidence required, so I will not fill that in.

What matters for the SiC story is that substrate capacity is a shared input across uses. A tight SiC substrate market matters for power device makers, and the same crystal underpins the RF families too. That is one more reason the pace of the 200mm transition matters beyond EV inverters.

What a procurement or planning team should ask

The book's discussion suggests a short list of questions when evaluating a SiC supplier or a SiC-based design.

• Where does the boule come from? A vertically integrated maker answers from its own crystal growth. A device maker without its own substrate depends on a merchant supplier, and Wolfspeed supplies an estimated 50% to 60% of that merchant market.
• Which wafer diameter is the part built on? Fabs at Infineon, STMicroelectronics, Wolfspeed, ROHM and onsemi run across both 150mm and 200mm, so the answer varies by product line.
• How is the cost claim derived? A 20% to 30% industry figure and a 50% company figure describe different starting points. One is a broad reference target, the other is a purpose-built line.
• Is the supplier's share figure comparable? Infineon's over 30% and 21.0% show that a share number without its category boundary is not a like-for-like measure.

The dependency that does not go away

The book's most useful point, to my mind, is that vertical integration does not fully escape the merchant concentration if the boule still traces back to a small number of crystal-growth facilities. Whatever strategy a device maker chooses, the physical bottleneck of the chain sits at the substrate. That is a planning fact more than a competitive one: capacity decisions in upstate New York and North Carolina become an input that makers on three continents have to plan around.

It is also why the sentence in the book about India is worth repeating. A country that builds the packaging layer first, as CDIL is doing in Mohali, is building the layer that is easiest to reach and least constrained. It does not yet address the layer where the constraint actually lives. I do not say that as a criticism. Packaging is a sensible entry point. It is just important to be clear about which part of the chain a given investment touches.

What to take away

SiC wins on physics: roughly three times silicon's bandgap and nearly ten times its breakdown field, worth an estimated 5% to 7% of EV range in an 800V traction inverter.

Its cost disadvantage against silicon lives in the substrate, grown by PVT above 2,400°C and limited by defect density. The move from 150mm to 200mm, with about 1.8x the area, targets a 20% to 30% industry-wide per-die cost reduction, and Wolfspeed targets 50% on a purpose-built, automated line.

Wolfspeed supplies 50% to 60% of merchant substrate, including to its rivals. Infineon competes on portfolio scale, and onsemi on vertical integration. For India, the packaging step is under way in Mohali, and the substrate layer is the open question.