The Back End Is Where India Started

Every chip that leaves a wafer fab is an unpackaged, untested die. It cannot be soldered to a board, it is electrically exposed, and nobody knows yet whether it works. The conversion from that bare die to a component you can actually buy happens mostly outside the fab, in a separate, high-volume and comparatively capital-light industry called outsourced semiconductor assembly and test, or OSAT. It is the least glamorous link in the semiconductor value chain and the one every packaged chip has to pass through.

I want to cover three things. First, how traditional assembly, test, mark and pack (ATMP) works and what drives its economics. Second, how the OSAT market is structured. Third, why this rung of the ladder, and not fabrication or advanced packaging, is where India has actually made concrete progress. The figures come from the book's back-end chapter, with a few references to its advanced-packaging chapter, and I keep its caveats.

What ATMP is, and why it became its own industry

A finished wafer is a disc carrying hundreds or thousands of individual die. ATMP is the sequence of back-end operations that turns it into the packaged, tested, branded part that ships to an electronics manufacturer. Firms that do this on contract for chipmakers without their own back-end lines are OSATs.

Why is it a separate industry? The book's answer is economic. A fab's cost is dominated by lithography, deposition and etch tools that carve silicon at nanometre precision. A back-end line's cost is dominated by materials (leadframes, substrates, mould compound, bonding wire), labour, and how well test equipment is used across many product families at once. Integrated device manufacturers such as Intel, Samsung and Texas Instruments have historically run both under one roof. The other model splits them and sends back-end volume to a specialist that can spread fixed assembly and test capacity across dozens of fabless and IDM customers at once. That second model produced the OSAT industry. Historically, assembly and test capacity has migrated toward lower-labour-cost, high-throughput geographies in Asia, which is why Taiwan, China, Malaysia and Korea host most of the leading OSATs' facilities.

The sequence in plain terms

Wafers are first thinned by back-grinding, then diced into individual die by sawing or laser cutting. Each die goes through die attach. In wirebond packages it is bonded to a leadframe or laminate substrate with adhesive. In flip-chip formats it is inverted and soldered face-down using an array of tiny bumps. The interconnect that follows, wirebonding on one branch and flip-chip reflow on the other, is the single choice that most defines the package.

The assembly is then encapsulated. For leadframe packages that is usually transfer moulding, in which heated epoxy is injected around the die and wires to form the familiar black plastic body. For substrate-based ball grid array and chip-scale formats it may be a smaller, localised cap. After curing, leadframe packages are trimmed and formed, and substrate packages get solder balls on the underside. Every unit is laser-marked with part number, lot code, date code and manufacturer, the data that distributors and automotive traceability audits rely on years later. Finally the part is tested, then packed, usually on tape and reel for automated placement.

Package formats follow the interconnect

Traditional back-end packaging is a family of formats distinguished mainly by how the die's pads reach the outside world. Wirebonding is the oldest and still the lowest-cost interconnect in volume use. Fine gold or copper wire, typically 15 to 25 micrometres in diameter, runs from each pad to a lead, at pad pitches of roughly 35 to 50 micrometres. It dominates microcontrollers, automotive ICs and power discretes, where cost and proven reliability matter more than density. Flip-chip inverts the die and connects it through solder or copper bumps, cutting the electrical path and supporting far higher pin counts. System-in-Package integrates multiple die and passives into one module, as in a smartwatch board or a wireless earbud.

Two points matter for what follows. The progression from wirebond to SiP is broadly from lowest to highest cost and density, but it is not a hierarchy in which flip-chip replaces wire. Wirebonding remains the largest interconnect category by volume because the automotive and industrial markets it serves are huge and do not need flip-chip density. And package format correlates with the maturity of the die inside. Wirebond QFN and small-outline packages carry mature-node logic and analog silicon: microcontrollers, power management, discrete transistors. Flip-chip BGA and CSP house leading-edge CPUs, GPUs and mobile processors, where the die itself is a front-end achievement beyond what a new manufacturing base can reach. An OSAT industry built first on wirebond, QFN, BGA and power formats is, by construction, aligned with the mature-node, automotive and power-electronics end of the market.

Where the economics really sit: test

If assembly gives a package its shape, test proves it works, and the book argues that test shapes OSAT business models more than assembly does. Final test checks every unit against its specification: parametric tests for voltage, current and timing, functional tests against known-good patterns, and speed binning to sort parts sold at several performance grades.

Burn-in is more selective and more consequential. It rests on the bathtub curve of failure rates: a disproportionate share of failures come in the earliest hours, then a long low plateau, then wear-out much later. Burn-in runs finished units under elevated electrical and thermal stress for a set period to force early failures inside the OSAT's factory instead of in the field. It is applied chiefly to automotive, industrial and defence parts. That makes the automotive and industrial segments, which wirebond QFN and power-module packages serve, structurally heavier on test and burn-in than the high-volume, lower-stringency consumer parts that dominate flip-chip CSP and SiP.

The economic point is that automated test equipment is typically the most expensive class of capital on an OSAT floor, and a tester configuration is often qualified to a single product family's test program. OSATs therefore cannot shift test capacity between customers as freely as they shift assembly capacity. Keeping expensive testers busy against a full order book is one of the most consequential and least visible drivers of margin. A firm running programs for dozens of customers can smooth utilisation across that book. A small, single-customer operation cannot. For SiP, where multiple die are integrated before they can be tested together, the industry relies on known-good die screening, because one defective die found only after final assembly can force scrapping every good part bonded beside it.

A concentrated top and a long tail

At its top, OSAT is a scale business run by a few firms large enough to operate dozens of high-throughput lines across several countries. ASE Technology Holding, headquartered in Taiwan, is the world's largest pure-play OSAT, with 44.6 percent of global OSAT revenue in TrendForce's 2024 ranking. It ships more than 25 billion packaged units a year from facilities in Taiwan, China, Malaysia, Korea and Europe. By its own reporting its shipment mix is roughly 45 percent flip-chip, 35 percent wirebond and 20 percent SiP. The book's advanced-packaging chapter puts ASE's 2024 packaging and test revenue at roughly US$19 billion.

Amkor, headquartered in the United States, is second, with annual revenue of $6.5 billion to $7.0 billion across more than 20 facilities and an estimated 14.5 to 15.5 percent revenue share. Together the two hold roughly 59 to 60 percent of global OSAT revenue.

I would draw two conclusions. Concentration here comes without the barriers of the front end. The book notes that entry barriers at the traditional-packaging end are comparatively modest, yet the top two still hold three-fifths of revenue, which suggests that scale, customer breadth and test utilisation are the real moat. Second, the layer beneath is fragmented and competes on cost, regional proximity to customers and format specialisation. The book flags the market share of that tier as unverified and I have not filled the gap.

The top of the market is being pulled away

The traditional tier and the advanced tier now behave differently. In advanced packaging, foundries are absorbing the highest-margin work, and OSATs increasingly act as overflow or licensed capacity. Amkor's June 2026 ten-year agreement for TSMC to buy local CoWoS capacity from its facilities is the clearest case, and I discuss it in the companion piece on advanced packaging. Amkor also guided 2026 capex of $2.5 billion to $3.0 billion, and ASE is breaking ground on six new facilities in 2026 across Taiwan, the US, Malaysia, Japan and Germany, including a roughly US$3.5 billion Kaohsiung Renwu advanced-testing facility targeted for phase-one completion in April 2027. Trade press reported ASE raising advanced-packaging quotes by more than 20 percent in mid-2026. Below the sub-40 micrometre tier, in flip-chip, wirebond, fan-out and test, the business stays a cost and capacity contest.

India: the back end first

India's semiconductor programme, the India Semiconductor Mission run by MeitY, launched with an outlay of 76,000 crore rupees, about $10 billion. The Union Cabinet has approved five commercial projects with combined investment above 1.50 lakh crore rupees, about $18.5 billion. Only one is front-end fabrication: Tata Electronics' 300 mm wafer fab with PSMC at Dholera, Gujarat. The other four are OSAT and ATMP facilities.

Micron's Sanand plant packages DRAM and NAND flash into ball grid array modules. It sits on a 93-acre site in the GIDC Sanand Industrial Estate, with a Phase 1 cleanroom of 500,000 square feet, and is expected to create about 5,000 direct engineering jobs and a further 15,000 indirect. Micron's memory die are made at its fabs in Taiwan, Hiroshima and Singapore and shipped to India for packaging. Tata's Jagiroad facility in Morigaon district is Northeast India's first major high-technology semiconductor investment, aimed at high-density flip-chip BGA and integrated SiP for automotive and mobile customers. CG Power's joint venture targets legacy QFN and BGA, power discretes and microcontrollers. Kaynes is the smallest by capital.

Summed across the four back-end projects, approved capital is roughly $7.32 billion (60,416 crore rupees). Combined approved output across the three projects that quote a per-day figure, Tata Jagiroad, CG Power and Kaynes, exceeds 69 million packages a day. The book notes that figure is derived by adding the approved targets, and that Micron's target is stated in volume terms and not per day.

Geography and ecosystem

Three of the four back-end projects, Micron, CG Power and Kaynes, are co-located at Sanand, with the Tata-PSMC fab at nearby Dholera. That concentrates India's early manufacturing base in one state. Only Jagiroad breaks the pattern. The book notes a wave of tier-2 supplier interest into Gujarat, including specialty gases (Air Liquide, Linde India, INOX Air Products), chemical purification (Kanto Corporation, Chememan) and substrate and PCBA capacity (AT&S Nanjangud, Syrma SGS). It treats that only as directional context, without the project-level financial detail of the five anchor projects, and I do the same.

The honest framing

India's pattern is not an anomaly. The book argues that every earlier manufacturing entrant of the past five decades, Malaysia and the Philippines from the 1970s and China more recently, built its first durable foothold in traditional back-end assembly and test before attempting front-end fabrication at scale, because ATMP's capital intensity and process-node exclusivity are a fraction of a fab's. Four of India's five approved projects follow that sequence. The Tata-PSMC fab is the outlier, needing far more capital and a longer road to output.

Two qualifiers matter. First, scale. Tata Jagiroad's $3.25 billion approved capex is smaller than either ASE's or Amkor's annual revenue, and none of the four projects is positioned to contend for global OSAT share. They are the first cohort of domestic facilities able to package chips for India's own automotive, industrial, mobile and memory demand, reducing the near-total historical reliance on assembly and test done abroad. Whether any scales into an export-oriented OSAT, as Taiwanese and later Chinese firms did, is something the book leaves open, and it marks forward capacity or export commitments beyond Phase 1 as unverified.

Second, content. All four projects package die and wafers fabricated elsewhere. Micron's memory die come from Taiwan, Hiroshima and Singapore, and the logic packaged at Jagiroad, by CG Power and at Kaynes likewise originates in fabs outside India. That is not a criticism. ATMP is a real, substantial tier of the value chain, employing tens of thousands of people and moving billions of dollars even at ASE and Amkor, which never touch a wafer fab. But it is accurate to call what India has built a real and fast-moving foothold in back-end assembly, not yet a front-end fabrication base.

What I take away

Back-end assembly is economically different from a fab. Materials, labour and test utilisation matter more than lithography, and that difference is why it split off as its own industry and why it is the easiest tier for a new entrant to reach.

Package format follows interconnect choice, and interconnect choice follows the die. Wirebond QFN and power packages serve mature-node, automotive and industrial demand, with heavier test and burn-in. That is the segment India's projects are aimed at.

The market is concentrated at the top, with ASE at 44.6 percent and Amkor at roughly 15 percent, but the moat is scale and test utilisation, not process secrecy. For India the test is not whether four plants exist but whether they reach the utilisation and customer breadth that make an OSAT profitable, and whether any moves toward export markets. On both, the evidence in the book is silent, and I would treat any confident forecast with caution.