When a server backplane fails at 112G per lane, the cause is rarely the chip. It is often the board: specifically, the resin and the copper foil that go into the press before any circuit is imaged. Laminate and foil rarely appear on a product specification sheet, yet they set the ceiling on the data rate a board can carry, and that ceiling is fixed upstream of the PCB fabricator by a short list of chemical formulators. This article looks at those materials, how the fabrication process turns them into a board, and what that means for signal integrity and supply concentration.
My figures come from the book's chapters on PCB fabrication and on signal integrity. Where the sources disagree, I keep the range and say so.
Same three raw materials, very different boards
A rigid FR-4 board etched to roughly 75 micrometre lines and a smartphone's any-layer HDI stack etched to 15 micrometres are built from the same three raw materials: copper foil, resin and glass cloth. What differs is the lithography, drilling and plating around them. Global PCB production across rigid, flex, HDI and package-substrate categories is reported above $80 billion a year, in an $80 billion to $85 billion band by IPC and Taiwan Printed Circuit Association reporting. That single figure spans a two-layer appliance board and a 32-plus-layer server backplane that differ in unit cost per area by an order of magnitude or more, so I would not read much into the aggregate.
Layer count is the main axis of complexity. Boards of 2 to 6 layers serve consumer appliances and simple industrial controls. Boards of 12 to 32-plus layers serve enterprise networking and 5G backplanes, where many signal, ground and power planes must be interleaved to control impedance and switching noise. Each added layer pair means another lamination press cycle, more drilling and another chance for misregistration, so layer count works as a rough proxy for both price and yield.
| Technology tier | Typical line / space | Via formation | Layers / segment |
|---|---|---|---|
| Standard rigid PCB | ~75 / 75 µm | Mechanically drilled through-holes | 2 to 6 (consumer); 12 to 32+ (enterprise, 5G) |
| HDI | ~50 down to 15 / 15 µm (mSAP) | Laser microvias, blind and buried | 1+N+1, 2+N+2, any-layer |
| IC package substrate (ABF) | ~5 / 5 µm | SAP semi-additive | Separate topic |
One inconsistency to note: this chapter gives ABF substrates at about 5 micrometres, while the dedicated substrate chapter reports 2 micrometres at the finest end and 5 at the upper end of its range. Both are consistent with a 2 to 5 micrometre band.
The manufacturing base is concentrated in East Asia. Taiwan hosts Zhen Ding Technology, Unimicron and Tripod. South Korea's Samsung Electro-Mechanics and Daeduck are major suppliers, particularly into consumer and automotive electronics. China's producers, including DSBJ and Shennan Circuits, have scaled into one of the largest by volume. Ibiden and Shinko in Japan appear in the same surveys but weigh more toward IC package substrates.
The signal integrity ceiling starts with the laminate
A PCB trace is not a perfect wire. It is a distributed transmission line, with a characteristic impedance set by trace geometry, copper thickness and the dielectric beneath it. Where that impedance changes abruptly, at a connector, a via, a plane split or a change in trace width, some signal reflects backward. The reflection shows up as ringing, overshoot or eye-closure at the receiver. As data rates climb, the margin for reflections shrinks, and two loss mechanisms start to decide whether a design works at all.
Conductor loss comes from the skin effect. At high frequency, current crowds into a thin layer near the copper surface, so effective resistance rises with frequency. Surface roughness compounds it, because a rough surface forces current along a longer path than a smooth one.
Dielectric loss comes from the laminate itself, quantified by the dissipation factor (Df, or loss tangent): how much signal energy the dielectric absorbs and turns into heat. Both mechanisms are governed, for the industry, by IPC-4101, which classifies laminates by glass transition temperature (Tg), decomposition temperature (Td), dielectric constant (Dk) and Df.
From FR-4 to low-loss: the laminate ladder
The practical consequence is that not every laminate supports every data rate. The book lays out a ladder.
Standard FR-4
Epoxy resin reinforced with woven E-glass cloth and clad with copper on one or both faces. It is the commodity baseline, with a Tg of 140 to 150°C and a Df of about 0.020 at 10 GHz. That is adequate for lower-speed digital logic and far too lossy for contemporary high-speed serial links.
High-Tg FR-4
Formulated with phenol-cured epoxy chemistry to push Tg above 170°C, and toward 200°C in the highest-performance formulations. Note what problem this solves: surviving repeated lead-free reflow peaks around 260°C without delaminating or softening. It does not reduce signal loss. This is a common confusion. A high-Tg board is more robust, not faster.
High-speed low-loss laminates
Built on polyphenylene ether (PPE) or polyphenylene oxide (PPO) resin systems rather than standard epoxy. Panasonic's Megtron 6 and Megtron 7 are cited as reference specifications, with Df of 0.0015 to 0.002 at 10 GHz, roughly an order of magnitude below standard FR-4, and Tg above 180 to 200°C. These are specified for PCIe Gen 5 and Gen 6 links and 112G Ethernet backplanes.
PTFE and ceramic-hydrocarbon
At the extreme end of the spectrum, 77 GHz automotive radar and satellite communications, dielectric loss on any epoxy-based system would be unworkable. Here the industry moves to PTFE and ceramic-hydrocarbon laminates, with Rogers Corporation the specialist most consistently cited. These are built for RF performance, not digital logic economics.
| Parameter | Standard FR-4 | High-speed low-loss (Megtron 6/7) |
|---|---|---|
| Glass transition (Tg) | 140 to 150°C | Above 180 to 200°C |
| Df at 10 GHz | ~0.020 | 0.0015 to 0.002 |
| Copper foil roughness (Rz) | Above 3.0 µm (standard ED foil) | Below 1.0 µm (HVLP foil) |
The copper foil matters as much as the resin
This is the point I think gets underweighted outside the industry. Signal loss at high frequency concentrates in a thin layer at the conductor surface. So a rough copper-to-dielectric interface adds loss regardless of how good the dielectric is. Standard electrodeposited (ED) foil, made by continuous electroplating onto a rotating titanium drum, has a surface roughness (Rz) above 3.0 micrometres. That is fine at lower frequencies. It becomes a measurable loss contributor once skin depth is comparable to the roughness profile, which the book puts at around 28 GHz and above.
Very Low Profile (VLP) and hyper-very-low-profile (HVLP) foils bring roughness below about 1.0 to 1.5 micrometres, depending on grade. That is why a genuinely high-speed specification pairs a PPE or PPO resin with HVLP foil. Neither improvement is sufficient alone. If you buy the expensive resin and leave the standard foil, you have bought less than you think.
There is a trade-off worth mentioning from the substrate side. In package substrates, the desmear step deliberately roughens the dielectric surface, at Rz of 0.2 to 0.5 micrometres, so that plated copper adheres. Roughness serves adhesion and hurts loss, and every high-speed material choice sits on that tension. I raise it as an observation, not something the book quantifies for boards.
Laminate selection is fixed at the design stage and cannot easily be changed after a board is qualified. A designer's choice of laminate supplier is therefore a choice of the ceiling on the data rate the board can support, and that ceiling is set upstream of the PCB fabricator.
Why the data rates force the material change
The book ties the material shift directly to the interfaces that drive it: 112G Ethernet backplanes, PCIe Gen 5 and Gen 6 links, HBM4's 1,024-bit memory bus, DDR5 running as fast as 8,400 MT/s and LPDDR5X above 8,500 Mbps. Those demand laminates with a Df an order of magnitude below legacy FR-4, foil roughness controlled to sub-micron tolerances, and package substrates that hold their electrical performance across every one of those interfaces.
At the same time, wide-bandgap power devices raise switching speed, and with it the dv/dt and di/dt that the power delivery network must absorb without radiating it through the chassis. A board that solves only the signal side, or only the power side, still fails. Reflections and rail noise both close the same eye diagram, and both compete for the same layout area and the same emissions budget. Whatever margin a lower-loss laminate buys still has to clear FCC Part 15, CISPR 32, BIS CRS and CE testing before the product can be sold. So signal integrity, power integrity and EMC have merged from three sequential late-cycle checkpoints into a single constraint that must be designed for from the first layout decision. A design that passes chamber testing only after an expensive respin has missed its market window.
HDI and mSAP: the fine-line frontier
Not every board needs low-loss materials. Some just need more routing in less area. High-Density Interconnect (HDI), governed by IPC-2226, is defined by a bundle of capabilities: microvias below 150 micrometres drilled by UV or CO2 laser, blind and buried vias, and trace width and space well below the 75 micrometre baseline.
The shift that enables this is from subtractive to semi-additive. A standard rigid board starts with thick copper foil, commonly around 30 micrometres, and etches away everything not part of the trace. The modified semi-additive process (mSAP) starts with an ultra-thin seed of about 2 to 3 micrometres, defines the pattern photolithographically, electroplates copper to thickness (commonly around 15 micrometres) only where needed, and quick-etches the exposed seed. There is far less copper to remove, so finer lines are possible on the same equipment.
| Process | Line / space | Microvia diameter | BGA pitch supported |
|---|---|---|---|
| Standard subtractive (30 µm foil) | ~75 / 75 µm | ~150 µm | Above 0.65 mm |
| HDI, general threshold | Below 35 / 35 µm or below 50 / 50 µm, per source | Below 150 µm | Fine-pitch BGA escape |
| mSAP / SLP | 25 / 25 down to 15 / 15 µm | 50 to 75 µm | 0.35 to 0.4 mm |
The HDI line/space threshold varies across the book's sources, one diagram cites 35 micrometres, the prose in the same file cites below 50, and the dedicated reference says below 35. I report the range, not a single figure.
Stackup architecture is the second axis. Sequential build-up constructions, written 1+N+1 or 2+N+2, add one or two laser-drilled build-up layers on each face of a conventional N-layer core. Any-layer HDI connects every layer to its neighbours through copper-filled laser microvias, so a BGA is not limited to the routing channels on its outer layers, a constraint that becomes binding well before minimum line width does on packages with ball pitches around 0.35 millimetres. The densest phone motherboards use this, under the label substrate-like PCB (SLP). At 15 micrometres line and space, SLP sits only one process generation from the roughly 5 micrometres of ABF substrates. The book is explicit that the overlap in lithography does not mean overlap in market or product scope.
Flex is a different branch. Flexible and rigid-flex boards replace glass-reinforced epoxy with polyimide film, typically 12.5 to 50 micrometres. Rolled-annealed copper, with an elongated grain structure that resists cracking, is mandatory for dynamic flexing such as a foldable phone hinge specified for more than 200,000 flex cycles. Electrodeposited foil, with a columnar grain, suits static or occasional flex. Coverlay film replaces liquid solder mask, which would crack. Nippon Mektron is documented as the leading global flex PCB maker, with Flexium and Interflex also cited. I mention it for completeness. It is the same lesson again: the material choice, not the process, sets the performance envelope.
Fabrication equipment: where the line and space figures come from
The line and space figures are not a design choice a fabricator can simply decide to meet. They are a function of which generation of equipment it has installed.
Imaging. Laser direct imaging (LDI) projects the digital layout onto photoresist with a 355 nanometre UV laser and dynamic optical alignment, with no physical film. That gets line and space down to 10 micrometres and improves layer registration, since there is no film to stretch or shrink. Orbotech (now part of KLA), Via Mechanics, Schmoll Maschinen and Hans Laser are the most cited vendors.
Drilling. Through-holes on a rigid board are cut by high-speed CNC drills. Microvias are laser-drilled, because no mechanical drill can reliably form a hole below about 100 micrometres at production speed. CO2 lasers suit glass-reinforced epoxy, where the longer wavelength couples into the resin and glass composite. UV lasers suit thin organic films, down to 20 micrometres at more than 1,000 hits per second. Mitsubishi Electric, Via Mechanics and Schmoll are the most cited.
Desmear and plating. Drilling leaves a smear of melted resin on the copper inside the hole, removed chemically, most commonly with a permanganate process. Pulse-reverse electroplating then builds copper on the walls. Alternating the current direction in short pulses gives more uniform wall thickness in high-aspect-ratio holes than continuous current, which matters directly for the yield of any board with fine microvias.
The supply chain is a short list
The book makes the concentration point twice, and I agree with it. Laminates capable of these Df and roughness specifications come from a small set of producers.
| Producer | Base | Role noted |
|---|---|---|
| Shengyi Technology, Sytech | China | CCL supply |
| Kingboard Laminates | Hong Kong and China | CCL supply |
| Panasonic Industry | Japan | Megtron series anchors high-speed low-loss |
| Taiwan Union Technology (TUC) | Taiwan | CCL supply |
| Rogers Corporation | United States | PTFE and ceramic-hydrocarbon RF materials |
A design team's signal integrity roadmap is therefore, whether or not it is treated that way, a supplier-concentration exposure. The book adds the equivalent on the power side, with SiC substrates from Wolfspeed, Coherent, ROHM, STMicroelectronics and SK Siltron CSS.
Where India sits
India's rigid PCB base is small and concentrated among AT&S India's Nanjangud facility (high-layer-count industrial and automotive), Ascent Circuits, Shogini Electronics and Genus Electrotech. What share of domestic demand they meet is contested. Published estimates run from roughly 12% to 35% of local consumption, and the book says the width of that range likely reflects differences in scope, whether the denominator is value, area or a narrower category like multilayer boards, more than a real disagreement about the manufacturing base. No single authoritative study reconciles it. I would quote the range, not a point.
The equipment is the second constraint. India is reported to import over 90% of its high-precision PCB machinery, LDI systems, laser drillers and plating lines, from Taiwan, Japan, Germany and China. Under the SPECS scheme and state ESDM programmes, AT&S India, Shogini and Ascent are reported to be upgrading toolsets for multilayer HDI. What share of machinery is made domestically is not established in the sources and is flagged as awaiting a dedicated MeitY audit. India also has no domestic high-speed laminate production noted in the book, which is a live gap in the national ESDM agenda.
What to take away
First, the data-rate ceiling of a board is set by its materials before any circuit is imaged. Standard FR-4 at Df of about 0.020 does not support PCIe Gen 5 and Gen 6 or 112G Ethernet. PPE or PPO low-loss laminates at 0.0015 to 0.002 do.
Second, resin and foil are a pair. A low-loss laminate with standard foil, above 3.0 micrometre roughness, wastes much of the gain, particularly above about 28 GHz.
Third, high-Tg is a reliability feature, not a speed feature.
Fourth, line and space figures depend on installed equipment as much as on design intent, and the equipment base is itself concentrated in a few countries.
Fifth, for India the gaps stack: a thin, contested domestic PCB base at 12% to 35% of demand, over 90% machinery import dependence, and no domestic path yet described for the laminates that decide the ceiling.