HBM3e and the Memory Wall: DRAM Oligopoly, HBM4 and Micron Sanand

Memory is the one semiconductor category where India's position fits in a single sentence: back-end only, one company, one site. Samsung Electronics, SK hynix and Micron Technology fabricate the overwhelming majority of the world's DRAM and High Bandwidth Memory (HBM), and every one of their front-end fabs sits outside India. What India has, as of mid-2026, is Micron's assembly and test plant in Sanand, Gujarat, which packages die that arrive as wafers from Micron's fabs abroad. I want to lay out why memory has become the tightest chokepoint in the AI accelerator supply chain, what changes with the HBM4 transition, and what Sanand does and does not represent.

Everything below is grounded in the memory chapter of my ESDM research book. Where the sources disagree, I keep the disagreement visible rather than picking a number.

Three kinds of memory, one supercycle

Memory splits into three families. DRAM is volatile working memory: the memory a CPU or GPU reads from and writes to continuously while it runs. NAND flash is non-volatile storage, now built as vertically stacked 3D arrays (Samsung calls its version V-NAND, Kioxia and SanDisk call theirs BiCS FLASH). HBM is a specialised form of DRAM in which several dies are stacked using through-silicon vias (TSVs) and mounted right next to an AI accelerator, instead of being reached across a conventional memory bus.

All three are inside what analysts call an AI-driven supercycle in 2026. The size of that supercycle depends on whose number you use, and the spread is wide. WSTS puts the 2026 memory category at $294.82 billion, up 39.4% year on year. SK hynix's own outlook says the memory market will exceed $440 billion inside a roughly $975 billion semiconductor market. TrendForce, as cited in secondary reporting, gives $551.6 billion. Persistence Market Research gives only $203.0 billion for 2026, growing to $403.2 billion by 2033 at a 10.3% compound rate.

That is a 2.7-fold gap for the same calendar year. My reading, and the book's, is that this mostly reflects scope: memory integrated circuits alone versus a wider category that includes modules and SSDs. It is not a real disagreement about demand. The book is clear that no reconciled total was found, so the honest use of these figures is as a directional order of magnitude.

What is not in dispute is the direction of the segments. Bank of America forecasts DRAM revenue up 51% in 2026 with average selling prices up 33%, and NAND revenue up 45% with prices up 26%. HBM is the smallest of the three by revenue and the fastest growing, at $54.6 billion in 2026, up 58%. The proximate cause is simple. AI data-centre buildout is pulling DRAM, HBM and enterprise SSD capacity all at once, faster than fabs can add it. DDR5 spot prices reportedly rose as much as 89% during 2026, and TrendForce projected server DRAM contract prices up more than 60% quarter on quarter at points in the year.

The DRAM oligopoly

DRAM is the most concentrated of the three at the front-end fab level. Samsung, SK hynix and Micron together control between 90% and 95%-plus of global output across the sources reviewed, with one TrendForce analysis putting it above 95%. The remainder is split between China's CXMT and Taiwan's Nanya, with CXMT far larger and rising faster.

Shares move from quarter to quarter and different sources use different methods, so I show two reported quarters side by side rather than blending them.

Two details stand out. First, leadership inside the top three is unstable. Samsung lost the DRAM revenue lead to SK hynix in Q1 2025, the first time since 1992, and took it back by Q4 2025. Second, CXMT is the clearest structural change underway. Its Q1 2026 share of 7.6% compares with 4.7% a year earlier. By mid-2026 it was reported running about 265,000 wafer starts per month, aiming for roughly 350,000 by the end of 2026 and about 500,000 by 2028, a level that would be close to 17% of global DRAM supply. It completed a large Shanghai listing in July 2026. It also sits on the US Department of Defense list of Chinese military companies, which complicates sourcing for Western customers.

The book is candid that it has little on the DRAM process-node roadmap across vendors. The one data point is that Micron's 1-gamma node is the base for its planned HBM4E product. I will not extrapolate beyond that.

NAND, briefly

NAND is less concentrated at the top, and its Japanese producers work in an alliance. Samsung led revenue share at 32.3% in Q3 2025 and roughly 29% in Q1 2026. SK hynix followed at 19.3% in Q3 2025. Kioxia posted 15.3% that quarter, passing Micron on 33.1% quarter on quarter growth, the fastest of any NAND producer in the period. SanDisk held 12.4% and Micron about 13%.

Kioxia and SanDisk operate a 25-year manufacturing alliance and jointly run what is reported to be the world's largest NAND fab base, in Japan. That makes Japan, not Korea, the largest single production geography for 3D NAND, even though Korean and American firms lead the revenue rankings. The race is now about layer count, because stacking vertically substitutes for lithographic shrinks that have become harder and dearer.

SK hynix and SanDisk are also developing High-Bandwidth Flash, which brings HBM-style near-processor stacking to NAND, with integration targeted around late 2027. It is a sign that the logic behind HBM is starting to spread beyond DRAM.

The memory wall

The reason HBM exists is architectural. AI accelerator compute has grown far faster than the bandwidth of the memory feeding it. One TrendForce estimate cited in the book has AI model compute growing about threefold over a two-year period while memory bandwidth over the comparable period grew only 1.6%. The consequence is that AI processors increasingly sit idle waiting for data, limited by memory rather than by their own logic.

Faster logic cannot fix a processor that waits on data. Only faster and closer memory can. HBM shortens the physical distance between memory and processor and widens the interface enormously. That is why HBM demand in unit and bit terms is reported to have grown over 130% in 2025, with growth above 70% projected for 2026, and why all three leaders have redirected capital toward TSV-stacked memory instead of simply adding standard DRAM capacity.

One thing I would flag on the chart above: the two figures come from the same analysis but cover "a two-year period" and a "comparable period", and the book does not give the base year. I have drawn them as an index so the shape is visible. Treat it as an illustration of the gap, not as a measured series.

HBM3e to HBM4: a redesign, not a speed bump

HBM3e is the current flagship generation and is expected to be about two-thirds of HBM shipments in 2026, even as HBM4 enters mass production in the same year. HBM4 changes the structure of the part.

• Interface. It doubles the interface width to 2,048 bits across 32 independent channels, with pin speeds of 11.7 to 13 gigabits per second, roughly double HBM3e's throughput.
• Bandwidth. More than 2.0 terabytes per second per stack in standard configurations and up to 3.3 terabytes per second in advanced ones.
• Base die. The passive base die under the DRAM layers becomes an active logic die, made on a 12-nanometre or 5-nanometre class logic process.

Samsung's demonstrated example is a 36-gigabyte, 12-high HBM4 stack combining sixth-generation 10-nanometre class DRAM core dies with a logic base die on its SF4 process, with 2,048 IO pins and 3.3 terabytes per second. The base die is what turns the stack into something closer to a co-processor. Customised, embedded-logic base dies are emerging as a real point of differentiation among the three vendors. All three began HBM4 sampling in 2025, with mass-production ramps through 2026. An HBM4E generation is mentioned across sources, but its specifications are not independently confirmed, so I leave them out.

The manufacturing chain adds a second concentration point. HBM stacks dies with TSVs and connects them to the base die through advanced packaging, and hybrid bonding is emerging as the technique for higher density and yield. As of the sources reviewed, hybrid bonding is not covered by current export controls on advanced semiconductor equipment, a gap policy analysts have flagged as a possible loophole. The DRAM dies still rely on immersion deep ultraviolet lithography. But the HBM4 logic base dies are fabricated at leading-edge logic nodes at merchant foundries such as TSMC. So HBM supply depends on the memory makers and on the leading-edge logic foundry market at once.

Who controls HBM

If DRAM is a three-firm oligopoly, HBM is closer to a duopoly with a strong third. SK hynix, Samsung and Micron together control an estimated 97% of global HBM wafer production. Within that group SK hynix led through the HBM3e generation.

In Q2 2025 SK hynix held 62% of HBM, Micron 21% (having overtaken Samsung that quarter) and Samsung 17%. Goldman Sachs expects SK hynix to keep more than 50% share through at least 2026, with Samsung clawing some back as major customers qualify its HBM3E stacks and its HBM4 output ramps. For HBM4 specifically, UBS projects SK hynix could hold roughly 70% of the HBM4 market tied to Nvidia's Rubin platform in 2026. That is a single projection, and it is sharper than the HBM3e-era share.

Micron's trajectory matters here because Micron is both a direct HBM competitor and the operator of India's only memory facility. Its HBM3E 12-high stacks deliver 1.2 terabytes per second and go into current accelerators including Nvidia's H100, H200 and Blackwell-class GPUs. It has since moved into high-volume HBM4, at more than 2.8 terabytes per second per stack, over double the previous generation. By the third quarter of its fiscal 2026 it had shipped more than $1 billion of HBM4 revenue, with the ramp running at roughly twice the pace of its earlier HBM3E 12-high ramp. HBM4E on the 1-gamma node targets volume production in calendar 2027.

Both HBM3E and HBM4 supply from Micron were reported fully booked through calendar 2026, with demand commitments extending into 2027 and 2028. Micron expects the HBM market to reach $100 billion by 2028, growing about 40% a year. That is the company's own forward projection, not an audited outcome, and I would read it that way. On spending, Micron raised its planned fiscal 2026 capital expenditure from $18 billion to $20 billion as of a December 2025 disclosure, and later reporting tied to strategic customer agreements cited guidance as high as $25 billion. The book reports both as stated at different points and does not reconcile them, and neither will I. Micron also expects DRAM and NAND bit shipments to grow about 20% in calendar 2026.

The one significant outsider in HBM is CXMT, and the gap is large. Its HBM output in 2026 is described as roughly second-generation equivalent, comparable to technology from around 2016, with HBM3-class output targeted only by the end of 2026 and competitive-yield volume not expected before 2028. The book attributes the lag to equipment access and to immaturity in TSV and hybrid-bonding yield, not to a lack of DRAM fabrication capability in general, where CXMT is scaling quickly.

Micron Sanand: what it is

India has no front-end memory wafer fabrication, no DRAM, NAND or HBM die production, as of mid-2026. Its presence in the memory value chain runs through one facility doing one job: assembly, test, mark and pack (ATMP). Micron's Sanand plant was inaugurated by Prime Minister Modi on 28 February 2026 and is described as India's first large-scale commercial semiconductor packaging plant. It packages and tests DRAM and NAND using wafers imported from Micron's fabs abroad, for data-centre, mobile and automotive customers. It does not fabricate memory die. HBM is not reported as part of its product scope in the sources reviewed.

The scale is significant by India's semiconductor standards even though it is only the back end. It arrives after two well-known setbacks, the 1980s fire at the Mohali fab and the collapsed Vedanta-Foxconn venture, and the sources broadly call it a credibility breakthrough. I agree with that framing, and with the qualifier that nearly every source attaches to it.

The qualifier is that Sanand addresses only the last stage of the chain. No source reviewed indicates a domestic memory wafer fab is imminent, given the capital intensity and technology concentration described above. The book also could not find a memory-specific import-dependency percentage for India. What it does document is that India's overall semiconductor market was about $38 billion in 2023, projected to reach $100 billion by 2030, with essentially all of that demand met through imports or imported-wafer assembly, since no domestic memory or logic wafer fab is in production.

The policy scaffolding around it

Government support has scaled up alongside Sanand, though only part of it is memory-specific. The India Semiconductor Mission began in 2021 with an outlay of Rs 76,000 crore. Ten manufacturing projects had been approved with cumulative commitments of about Rs 1.60 lakh crore, plus four more units under a further Rs 4,600 crore outlay. ISM 2.0 was announced with Rs 8,000 crore in the Union Budget for 2026-27, the largest single-year outlay since 2021, focused on equipment and materials, chip design and indigenous IP. That signals an intended move beyond assembly and packaging. Packaging incentives are reported at up to 35% of project cost for advanced packaging and up to 25% for conventional, but that comes from an aggregated secondary source and should be read as indicative.

The Design Linked Incentive scheme was supporting 24 chip design projects as of January 2026, with 16 tape-outs completed and 6 ASIC chips fabricated. The Electronics Components Manufacturing Scheme, launched in April 2025 with a Rs 22,919 crore outlay, had attracted Rs 1.15 lakh crore in investment commitments by September 2025.

None of the other approved projects is confirmed as memory-specific. The Tata Electronics and PSMC fab under construction in Dholera is a logic fab of roughly 50,000 wafers per month and about Rs 91,000 crore. Tata's Assam OSAT, Kaynes Semicon's Gujarat OSAT, the CG Power and Renesas OSAT venture, and the HCL and Foxconn OSAT venture in Uttar Pradesh are general assembly and test capacity. So India's position in memory is back-end only, single company, single site. A hard-won entry point, but the front-end economics sit outside India's industrial base.

What to take away

• DRAM is a three-firm oligopoly at 90 to 95%-plus of output, with CXMT the fastest-rising challenger at roughly 5 to 8% in the quarters reviewed.
• HBM is more concentrated still, about 97% of wafer production at three firms, and SK hynix is projected near 70% of the HBM4 market tied to Nvidia's Rubin in 2026. That is one projection, not a settled number.
• HBM4 doubles the interface to 2,048 bits and puts an active logic die under the stack, which adds a leading-edge foundry dependency to an already tight chain.
• Market-size totals disagree by 2.7 times across four sources. Use them as an order of magnitude only.
• Sanand is real, sizeable and back-end. It handles DRAM and NAND packaging from imported wafers, not HBM and not wafer fabrication.

The practical reading for anyone tracking India's semiconductor plans is to separate credibility from capability. Sanand proves that a global memory maker will build and staff a large facility in India. It does not move India up the part of the chain where the oligopoly sits.