Glass-Core Substrates and 3D Interposers

Two technologies are supposed to carry AI packaging past its current limits: a substrate that does not warp, and a chip-to-chip bond that no longer needs a solder bump. Both are real. Both are also much less proven in the public record than the roadmaps built on top of them tend to assume. This article is about the first of them, glass-core substrates, and the second in its next phase, deeper 3D hybrid bonding. I will lean hard on the hedges in my source material, because on this topic the hedges are most of the story.

The short version of the book's own finding is unusual for an industry report: the core glass-core claims rest on one paragraph in one source document. That is not evidence the claims are wrong. It is evidence that the public record has not yet said much. Where I quote numbers below, I will say which ones come from where.

Why the top of the package stack is running out of room

Start with the physics, established in the ABF and BT substrate article. Silicon expands at about 2.6 parts per million per degree Celsius. The organic ABF and BT dielectrics under it expand three to six times faster. Every reflow cycle at roughly 260°C turns that mismatch into warpage. Substrate makers manage it with symmetric stackups, low-CTE cores and dummy copper pours, but they do not eliminate it. The book identifies where those mitigations stop being enough: AI chiplet packages larger than about 100 millimetres by 100 millimetres.

The packaging side describes the same ceiling from another angle. TSMC's CoWoS-L embedded-bridge platform is reported to approach roughly 5.5 times standard reticle area by 2026, because the largest multi-die AI accelerators have outgrown what a single silicon interposer or a conventional organic stack-up can hold without unmanageable warpage. One chapter reads it as materials science, the other as an area budget. Both arrive at the same conclusion: the organic dielectric that has served every FC-BGA package to date is approaching a size class it was not engineered for.

On its own that would be a slow-moving materials problem. It is not slow, because a second pressure hits the same layer. Organic substrate supply has tightened sharply under AI demand. The book reports ABF substrate lead times of 16 to 24 weeks as of mid-2026, a supply-demand gap estimated at roughly 10% in the second half of 2026 widening toward roughly 21% in 2027, and Ajinomoto reportedly raising ABF film prices by around 30% amid the shortage. Those figures describe the organic incumbent, not glass. But they change the economics of displacement. A next-generation substrate does not have to beat ABF on cost when ABF is scarce, slow to obtain and getting more expensive at exactly the segment where the largest packages strain it hardest.

I think this dual pull is the most useful framing in the whole topic. Most materials transitions have one driver, a performance ceiling. Here there are two, and neither alone would force a switch on any particular timeline. Organic substrate makers have handled CTE mismatch through stack-up engineering for years, and shortages usually resolve through capacity investment, not substitution. The coincidence is what strengthens glass's case. A stronger case is still not a well-evidenced one, as the next section shows.

What glass core claims, and what backs it

The technical case for glass rests, in the two documents assigned to this topic, on one short passage describing glass-core substrates as under development by Intel, Samsung and Absolics to overcome the warpage and planarity limits of organic ABF in the largest AI chiplet packages. Nothing contradicts it. The packaging manual, which covers 2.5D interposers, embedded bridges and hybrid bonding in depth, does not mention glass core at all, so it neither confirms nor disputes it. The book's earlier substrate chapter, working from a wider base of three documents, reached the same finding: the glass claims appear in only one of three, uncorroborated by the other two.

What that one source claims is specific and physically coherent. Glass is reported to offer near-zero surface roughness, below 0.5 nanometres. Its CTE can be tuned to match silicon's roughly 3.0 ppm/°C directly, instead of narrowing the gap the way low-CTE organic cores do. And its thermal stability is reported to eliminate substrate sag during 260°C reflow, instead of merely constraining it. Each claim maps to a limit of the organic substrate. Roughness governs how finely copper can be resolved and how well it adheres. CTE mismatch is the root cause of warpage. Thermal stability under reflow is what symmetric stackups and dummy copper pours try to approximate. If the claims hold, glass is not an incremental fix. It is a different approach to the same three problems, one that does not need the compensating engineering organic substrates depend on.

The row that matters most is the fourth, and neither the two documents behind this article nor the three behind the substrate article addresses it. The semi-additive process that delivers the 2 micrometre geometries big FC-BGA packages need was not just adapted to ABF. Its laser wavelengths, its desmear chemistry and its electroless copper seeding were developed around ABF's optical absorption, chemical reactivity and surface energy. Glass is a different material. My own reading, as general technical background and not from the book: glass does not absorb organic-resin laser wavelengths in the same way, it does not respond to permanganate desmear, which targets epoxy, and its surface chemistry for copper seeding at ABF's panel scale is unproven. None of that says glass cannot be processed. It says the source material does not describe how, and a reader should not assume the manufacturing question is solved just because the property question has been described. In the book's phrasing, that gap is arguably the single largest open question between the glass-core claims and a shippable FC-BGA-scale substrate.

Intel, Samsung, Absolics: three names, one data point

The glass-core source names three developers without distinguishing among them. No company-specific approach, product or timeline attaches to any of the three. On the substrate chapter's wider base, same result. Taken alone, that would leave a reader with three names and no way to rank them.

The book's packaging chapter closes part of the gap for one company, drawing on a different and broader source set that includes Intel's own newsroom disclosures, a 2026 industry advanced-packaging outlook and a policy analysis of the ABF chokepoint. It reports that Intel cited its Clearwater Forest product as a January 2026 production milestone on glass substrates. It assesses the technology as a whole at a technology readiness level of roughly 4 to 5, a research-to-production transition point and not a mature process. It puts current glass-core pricing at an estimated two to five times organic substrates, with cost parity not projected until roughly 2028. It identifies Corning as the glass supplier most visibly associated with the effort, and it attributes a further advantage to glass: because glass supports laser bonding and debonding during processing, it carries a lower reported risk of chip breakage during certain handling steps.

The book treats those figures as reported, cross-chapter facts, not independently re-verified findings, and I am doing the same. That matters for what can honestly be said about each company.

Read plainly, only one of the three has a dated, named production milestone anywhere in the book, and even that comes from a chapter drawing on sources that were not re-verified here. A reader tempted to treat "Intel, Samsung and Absolics are developing glass-core substrates" as three roughly equivalent and roughly simultaneous efforts should resist that. The evidence supports naming all three as participants and supports almost nothing about how they compare. The same pattern showed up in the organic substrate maker landscape, companies named as participants without the revenue, capacity or timeline data to rank them, and here it recurs one layer further out on the roadmap, where the uncertainty is naturally greater because none of the three has a general-market product.

One more practical point on what glass changes. Because glass supports laser bonding and debonding during processing, the book's packaging chapter reports a lower chip-breakage risk than organic substrates in certain handling steps. That is a process advantage independent of warpage. It is also one more claim I would file under reported and unverified until a second source confirms it, since it comes from the same broader source set as the Intel milestone.

The unifying point across all of these claims is that they are physically plausible, which is different from being demonstrated at production scale. Plausible mechanisms are where every next-generation material starts. Most of them still have to pass through yield, cost and qualification stages that the public record on glass has not yet described.

Beyond today's hybrid bonding

The second track is 3D direct hybrid bonding. The mechanics are already established in the book's packaging chapter: room-temperature dielectric-to-dielectric contact, then an anneal at 300 to 400°C that drives copper-to-copper atomic interdiffusion. The process demands sub-0.5 nanometre CMP flatness, single-digit-nanometre copper recess control and ISO Class 1 cleanroom discipline, because a single 100 nanometre dust particle can void several bond pads at once. The clearest production proof point is AMD's second-generation 3D V-Cache at a reported production pitch of roughly 9 micrometres.

That number is the useful one to think about. It is a pitch chosen for yield and cost, not the technology's density ceiling. Generic engineering literature cites sub-3 micrometres and, on longer roadmaps, sub-1 micrometre. The book reports industry roadmaps tightening from 9 micrometres toward roughly 0.8 to 1.5 micrometres for next-generation applications, with sub-1 micrometre a longer-horizon target. Set beside the other packaging platforms, the trend is legible: each generation has closed roughly an order of magnitude of pitch.

The harder-to-quantify part is not the pitch number. It is what the book calls the constraint in front of it: logic-on-logic stacking, where an entire compute die is bonded onto another active compute die, not cache onto logic as 3D V-Cache does today. That is a much harder thermal problem. Removing heat from a die buried under another active die, with no microbump standoff and no underfill flow channel to help, needs advances in backside power delivery and thermal interface materials that the book describes as still evolving in step with the packaging itself. So interconnect density could tighten past today's roadmaps and still not produce shipping logic-on-logic products, if cooling lags the bonding physics. Intel's Foveros Direct and TSMC's SoIC are the two platforms named on this frontier, with no product name, date or yield figure attached. That is what a technology at the pathfinding stage looks like, as against the production ramp that 2.5D interposers and cache-on-logic bonding have already reached.

Are the two roadmaps converging?

Both tracks aim at the same product class: the largest AI accelerator packages, up to roughly 5.5 times reticle area on one platform and above 100 by 100 millimetres on the substrate side. Glass is meant to give that package a base that does not warp. Deeper hybrid bonding is meant to let it stack more silicon, more densely, on top. It is tempting to conclude they are being engineered toward each other, a glass core under a hybrid-bonded logic-on-logic stack.

No source makes that connection. The glass source treats glass as a substrate development independent of packaging architecture. The packaging manual never mentions glass. And the book's packaging chapter, while it names Corning and Intel's Clearwater Forest milestone, does not say what sits on top of Intel's glass substrate: a hybrid-bonded stack, a conventional flip-chip die or something else. The book flags this convergence as its own analytical reading, and I want to be equally clear that it is a reading, not a documented plan. What would confirm it is a single disclosed product pairing a glass core with a hybrid-bonded logic-on-logic stack. None is identified. The two tracks may be qualified independently for years, especially if the manufacturing-compatibility questions above are not yet resolved even for organic-class packaging.

There is one argument for convergence I find sound, and it is physical. Every step to tighter hybrid-bonding pitch makes the die stack above the substrate taller, heavier per unit area and more thermally concentrated. All three worsen the warpage the organic substrate has to absorb. So as hybrid bonding advances, the case for a better base layer strengthens, whatever glass's own thin source base says. That is the closest the evidence gets to explaining why both technologies sit on the same future-horizons agenda.

What to take away

The direction is sound and the evidence is thin, and both statements need to sit together. The direction is sound because the organic CTE ceiling and the ABF supply squeeze are real, documented and arriving at the same time. The evidence is thin because the glass physics rests on one source, only one of three named developers has a dated milestone, and the process-compatibility question is unanswered.

For anyone using this for procurement or investment, I would treat the source base as a list of open questions and not as answers. The ones I would ask first: how SAP-class lithography, laser drilling and desmear adapt to glass; what yield Intel's Clearwater Forest substrate runs at; whether the 2x to 5x cost multiple and 2028 parity date apply to specific implementations or to the class; and what actually sits on top of a glass core in shipping product.

For hybrid bonding, the number to watch is not the pitch. It is when someone ships logic-on-logic, because that is where the thermal constraint decides how far the density curve can run.