Sand to Wafer: Czochralski Growth and a Five-Company Oligopoly

Every logic and memory chip starts as a few kilograms of purified sand. That is the tidy version. The untidy version is that between the sand and the wafer sit three separate industries: a chemical refining business, a crystal-growing business, and a finishing business that polishes a 300 millimetre disc to atomic smoothness. Five companies sell almost all of the result. Two of them are Japanese and account for about half of the world's 300mm supply.

I want to trace that chain in process order, explain why the crystal-pulling step is harder than it sounds, and then look at why the wafer market has stayed at five effective suppliers for the entire 300mm era. The facts here come from the semiconductor materials chapter of my ESDM research book, which draws on SEMI standards, SUMCO and Shin-Etsu filings, and METI data. Where the book marks a number as unconfirmed, I keep that hedge.

From quartzite to electronic-grade polysilicon

High-purity quartzite, which is silica (SiO2), is reduced in an electric-arc furnace by reacting it with carbon at high temperature. The product is metallurgical-grade silicon, roughly 98% pure. That is good enough for aluminium alloying. It is nowhere near good enough for a transistor, because at 98% purity the metal and dopant contamination sits many orders of magnitude above what a device tolerates. Everything after this point exists to close the purity gap.

The Siemens process

The standard route is the Siemens process. Metallurgical silicon is reacted with hydrogen chloride to make trichlorosilane, HSiCl3, usually written TCS. TCS is a liquid, and unlike solid silicon it can be purified by fractional distillation. It passes through several distillation columns in series, each stage stripping out boron, phosphorus and metals until the compound reaches sub-parts-per-billion purity. The purified vapour is then decomposed by chemical vapour deposition onto electrically heated silicon filaments held at about 1,100°C inside a sealed reactor, often called a bell jar. Silicon deposits layer by layer until the filament has grown into a dense polysilicon rod.

An alternative, the granular fluidised bed reactor process, deposits silicon continuously onto fluidised seed particles instead of static filaments. Some producers use it as a lower-energy option to batch Siemens reactors.

Either route yields electronic-grade silicon, polysilicon refined to 99.9999999% purity. The industry writes that as 9N to 11N. This is a semiconductor-specific bar. Solar-grade polysilicon is typically refined to a substantially lower floor because a photovoltaic cell tolerates carrier-lifetime losses that a logic transistor cannot. One stray metallic atom per billion silicon atoms can create an unwanted energy level inside the bandgap, changing carrier lifetimes and leakage, and the damage shows up as yield loss several process stages later.

The refining base is small. Hemlock Semiconductor in the United States, Wacker Chemie in Germany, OCI in South Korea and GCL-Poly in China are the names most consistently cited as key suppliers of Siemens-process electronic-grade polysilicon. Refining capacity overall is concentrated in China, the United States, Germany, Japan and South Korea.

Czochralski growth: pulling a crystal out of a melt

Polysilicon is clean but structurally useless. It has to become a single, defect-controlled crystal, and the method used for essentially all mainstream logic and memory silicon is the Czochralski process.

Polysilicon chunks are melted in a high-purity quartz crucible at about 1,425°C under an inert argon atmosphere. A small monocrystalline seed is dipped into the melt and slowly withdrawn while the seed and crucible rotate in opposite directions. As the seed rises, atoms from the melt solidify onto it in the same lattice orientation. The result is a cylindrical single-crystal ingot called a boule, which can reach roughly two metres in length at 300mm diameter, or 450mm in early pilot lines.

Why the magnetic field matters

The base process has a problem. The melt sits in a quartz crucible, and oxygen from the crucible walls dissolves into the growing crystal. Magnetic Czochralski adds strong superconducting magnetic fields around the crucible during pulling. The field damps convection currents in the melt, which controls how much oxygen enters the crystal and how evenly it spreads through the ingot. Oxygen content affects a wafer's mechanical strength and its electrical behaviour under thermal cycling. So I read magnetic Czochralski as a precondition for the tighter defect specifications advanced logic and memory now demand, not a cosmetic refinement. Industry benchmarks cite finished 300mm ingots exceeding 400 kilograms, though my source flags the precise modern maximum as unconfirmed because public technical literature is inconsistent.

Finishing: the boule is not yet a wafer

Growth gives a cylinder. Finishing gives a substrate. The ingot is ground to a uniform diameter, then sliced with diamond-wire multi-wire saws, where a single continuously moving diamond-coated wire threaded through hundreds of parallel cuts produces discs about 775 micrometres thick. Lapping removes saw damage and flattens the surface. Then chemical-mechanical polishing with a colloidal silica slurry combines chemical etching and mechanical abrasion to reach a mirror finish with root-mean-square roughness below 0.1 nanometres. At that scale the remaining texture is measured in atomic layers.

Three substrate classes from one crystal

The finished substrate is not always a bare polished wafer, and this matters for the market structure later. For demanding logic nodes, fabs specify epitaxial wafers, which are prime polished wafers with an extra single-crystal silicon layer grown on top by chemical vapour deposition, built for the ultra-low defect density that EUV lithography needs. A third variant, silicon-on-insulator, inserts a buried oxide layer beneath a thin top silicon layer. RF-SOI and fully depleted SOI, made through processes such as Soitec's, are valued in RF front-end chips because the insulating layer reduces parasitic substrate loss.

Each class is effectively a separate qualified product line, with its own recipe, defect budget and customer base, even though all three start from the same CZ boule. A supplier at the advanced end is not selling one commodity called silicon wafers. It is running parallel lines calibrated to each customer's node.

Two rows are unpublished in my source, and I have left them that way. Flatness and roughness are proprietary values that vary by product grade and are not disclosed at the same public-standard level as dimensional tolerances. What the table does show is that even the dimensional tolerances are fractions of a millimetre on a 300 millimetre disc, held wafer after wafer across a run that a single fab can consume in hours.

The oligopoly: five companies, more than 90% of revenue

The crystal physics and finishing above are hard enough that the 300mm wafer market has consolidated tightly. Five companies supply more than 90% of global 300mm wafer revenue: Shin-Etsu Handotai (a division of Shin-Etsu Chemical, Japan), SUMCO (Japan), GlobalWafers (Taiwan), Siltronic (Germany) and SK Siltron (South Korea). Shin-Etsu Handotai holds approximately 30% share and is the largest silicon wafer supplier in the world. SUMCO follows at roughly 20%. The two Japanese suppliers together account for roughly half of global 300mm supply, inside a market that was already concentrated.

Why a new entrant cannot simply build a line

Shin-Etsu supplies prime polished wafers, epitaxial wafers and SOI substrates engineered to sub-angstrom flatness and defect densities below 0.05 defects per square centimetre. Those specifications target EUV-based logic foundries including TSMC, Intel and Samsung, along with the major memory makers. Hitting them at fab volumes takes decades of know-how in crystal defect control, oxygen distribution and polishing uniformity. It is not something a well-funded newcomer buys off the shelf.

The bigger barrier is qualification. A new supplier must pass a multi-year, multi-billion-dollar qualification cycle with each foundry customer before a single lot enters production. The reason is straightforward. A wafer-level defect that escapes detection can invalidate months of downstream work on chips that may already be worth many times the wafer itself. So the barrier has two layers: capital for crystal-growth and polishing equipment, and customer-by-customer qualification on top. In my reading, that pair is what has held the market at five effective suppliers while fab capacity kept growing.

What the oligopoly means for a country building a fab

The wafer layer is one of three concentration layers in the materials chain. Above the mineral layer and the specialty-chemical layer, wafers are the most visible, because a fab's largest recurring input is a box of them. I will cover the chemical and mineral layers separately, but the wafer story already carries a lesson for a country building from a low base. A fab can be well capitalised and still depend on a foreign wafer supplier that has spent decades qualifying against defect specifications a newcomer cannot match quickly.

India's materials dependence shows up here. My source says India relies on imports for effectively 100% of its electronic-grade polysilicon, and it marks domestic wafer substrate manufacturing as a capability not yet established, with no concrete roadmap documented. That is a capability gap, closer to non-transferable process learning than to a purchasing problem.

Why this business is closer to chemistry than metallurgy

People tend to picture wafer making as a metals business: melt something, pull something, cut something. The early stages are closer to specialty chemistry. The reason is the purity target. Trichlorosilane distillation to sub-parts-per-billion levels is a chemical engineering problem, and the deposition onto filaments at about 1,100°C is a chemical vapour deposition step. A refiner's competitive position is its yield curve, meaning how much of the input trichlorosilane ends up as in-spec rod. That number is built over years of tuning distillation stages and deposition control, and it does not move with a licence.

This is also why the polysilicon stage stays concentrated among Hemlock, Wacker, OCI and GCL-Poly even as total semiconductor demand has grown for decades. A new entrant is not competing against a capital budget. It is competing against accumulated process learning inside existing reactor fleets. The same dynamic, capital plus non-transferable know-how, repeats at every later stage of the chain, from crystal growth to polishing to the chemistry a fab uses.

Solar-grade is not a shortcut

One question I hear is whether the large solar polysilicon industry gives a country a quick route into electronic-grade material. The source suggests it does not. Solar-grade polysilicon is typically refined to a substantially lower purity floor, because a photovoltaic cell can live with carrier-lifetime losses a logic transistor cannot. The 9N to 11N electronic-grade specification is a separate bar, so capacity built for one does not automatically serve the other.

What the specification table implies

The table above gives dimensional tolerances that look loose to a casual reader: plus or minus 0.20 millimetres on diameter, plus or minus 20 micrometres on thickness for prime wafers. Set against a 300 millimetre disc, those are small fractions. What is harder to see from the table is the pair of rows that are missing. Flatness and surface roughness, the values that most directly tie to lithography yield, are not disclosed publicly at the same level. They vary by product grade and are treated as proprietary.

That silence is informative. When the parameters that matter most are held back, the supplier relationship is not a catalogue purchase. It is a negotiated, customer-specific specification, and that is where qualification power comes from. It also means outside analysts, including me, should be careful about comparing suppliers on the numbers that are public. The public numbers are the ones that do not differentiate.

Where the product lines split

The three substrate classes, prime polished, epitaxial and silicon-on-insulator, come from the same crystal but diverge from there. Epitaxial wafers carry an additional single-crystal layer for the low defect density EUV processes require, and the edge exclusion zone is tighter, 1.0 millimetres against 1.5 millimetres for prime polished in the table above. SOI adds a buried oxide layer and is valued in RF front-end chips because the insulator reduces parasitic loss, which connects this article to the compound semiconductor layer in a handset. Each class is a separate qualified line, so a supplier that is strong in one is not automatically strong in the others.

Qualification as the real moat

I want to spend a moment on the qualification argument, because it is the part of the oligopoly that is least visible and most durable. A fab cannot accept a new wafer supplier on the strength of a data sheet. It runs a qualification, which in my source is described as a multi-year, multi-billion-dollar cycle per foundry customer. The cost is not the wafer. It is the risk. A wafer defect that escapes inspection can invalidate months of fabrication on chips already worth many times the wafer. The customer has every incentive to stay with a supplier whose defect behaviour is known.

This produces a market where incumbents are protected not by patents or regulation but by the customer's own risk calculus. It also explains the pairing at the top. Shin-Etsu Handotai at about 30% and SUMCO at about 20% are the two largest, and together they account for roughly half of 300mm supply. My supply-chain risk chapter cites the same concentration from a different angle, putting Japan at over 50% of 300mm silicon wafers. I read that as an agreement between two sources, not as a new number.

Why five companies is a resilience problem

From a buyer's perspective, five suppliers can sound like plenty. The complication is that each fab qualifies specific suppliers for specific product lines, so the practical choice set for a given process can be much smaller than five. Moving volume from one supplier to another is not a purchase order. It is a new qualification. That is the mechanism by which a market that looks competitive on paper behaves like a chokepoint in practice.

The wafer layer also sits above two other layers of concentration, specialty chemicals and critical minerals, and a buyer of a 300mm wafer is exposed to all three at once. I treat those in companion pieces on photoresists and on gallium and germanium, and the wafer story is the one that is easiest to see because the boxes arrive at the fab door.

What to take away

Three points. First, purity is set upstream of the crystal: 9N to 11N polysilicon from a handful of refiners is the entry ticket. Second, the Czochralski pull, with magnetic field control of oxygen, and the finishing steps, are individually demanding, and they split into three qualified substrate lines. Third, the market answers that difficulty with concentration. Five companies, two of them Japanese, supply over 90% of 300mm revenue, and the barrier that keeps it that way is multi-year qualification with each customer, not equipment cost alone.