Analog ICs: Why Analog Does Not Scale With Moore's Law

Two chips can be built in the same fab in the same week and still play by completely different economic rules. A logic processor is designed to be made obsolete by its successor within a product cycle or two. An analog voltage reference can still be the right part to design into a new product a decade later. Confusing the two is the fastest way to misjudge where an IC company's moat, and its risk, actually sit.

The question I want to answer here is the one the book puts in its chapter on integrated circuits: why does analog not scale with Moore's Law? The answer is physical, and it then cascades into design methods, product lifecycles, catalogue strategy and even who owns the fabs.

Three businesses that share a wafer

An integrated circuit is at least three products. A logic IC computes. An analog IC senses, regulates or amplifies a continuous physical quantity. A mixed-signal IC does both, translating between the two. The book treats this split as a description of how a company makes money, because required capital, design cost curves, product life and the decision to own or rent a fab all differ by category.

What logic gets from a smaller node

Logic ICs (CPUs, GPUs and the systems-on-chip that combine them with memory controllers, image processors and basebands) have a simple design objective: switch as many transistors as possible, per unit area and per unit energy, at the highest sustainable clock. That is why logic follows Moore's Law almost literally. A transistor one generation smaller is, to a first approximation, a faster, lower-power copy of the same digital building block, so shrinking the node is most of the roadmap.

Samsung Foundry's 3nm node gives a concrete measure of what that shrink is worth. Samsung was the first foundry to bring gate-all-around transistors to commercial production, in June 2022, marketed as Multi-Bridge Channel FET (MBCFET). Against its own prior 5nm FinFET node, Samsung's comparison is:

Those are gains a logic product gets mostly for free, in the sense that the design intent is unchanged. The bill comes elsewhere. Samsung's 3GAP reports an SRAM bitcell of roughly 0.0199 square micrometres and needs more than 20 extreme ultraviolet mask layers, each adding cost and yield risk. Leading-edge R&D, mask sets and verification costs escalate steeply with each generation, and only a product with enough unit volume can amortise them. That is why logic has consolidated around a short list of high-volume families and pushed towards the fabless model faster than any other IC category.

Why analog does not get the same ride

Analog ICs cover voltage references, operational amplifiers, low-dropout (LDO) regulators, comparators and the analog front ends that condition a sensor's raw output. Their performance is bounded by device physics that a smaller transistor does not automatically improve. Three phenomena matter most:

• Transistor matching. Precision circuits depend on two devices behaving alike.
• Thermal and flicker noise. These set the floor on how quiet an amplifier can be.
• Parasitic capacitance. It limits bandwidth and adds error in ways layout has to manage.

None of them shrink in proportion to the digital speed gain from a smaller node. A smaller node can make a logic gate faster and cheaper almost as a side effect. It does not, in the same automatic way, make an amplifier quieter or a voltage reference more stable. The book adds that every analog block has to be re-verified against noise and matching behaviour close to from scratch on a new node. Porting analog to a smaller process is therefore a far less mechanical exercise than porting digital.

A craft, not a push-button flow

The digital pipeline, from register-transfer-level code through synthesis, place-and-route and static timing analysis, is a highly automated flow that turns a functional specification into a manufacturable layout with little manual intervention. Analog design has never automated to that degree. AI-driven tools such as Cadence's Virtuoso Studio target the gap by automating placement and parameter exploration, but transistor-level analog layout remains substantially closer to specialist craft than to a push-button flow. That is a large part of why analog and mixed-signal design talent commands a premium over digital talent.

I think this is underrated as an explanation of analog's staying power. If a design flow cannot be automated and re-run on a new node at low marginal cost, then redesigning every product cycle is simply not economic. The incumbent part, once it works, stays.

Longevity is the business model

Because an analog part's core function does not depend on the newest node, analog ICs cluster on mature process technology, broadly 180nm and larger, the same territory the book places discrete power semiconductors in. They can stay in production, unchanged, for years after a comparable logic part would have been replaced. A logic SoC is redesigned essentially every product cycle because a faster, denser competitor is always one node away. An LDO regulator has no equivalent forcing function: nothing about a smaller node obliges a designer to replace a part that still meets its noise and accuracy specification.

The catalogue strategy follows directly. A logic vendor puts its engineering into a handful of flagship parts per generation, because that is where the volume, and therefore the return on a leading-edge mask set, lies. An analog integrated device manufacturer does the reverse. Since so many qualified analog parts never need redesigning on a newer node, the rational move is to keep building a broad catalogue across voltage references, op-amps, LDOs and application-specific signal-chain variants. Each part wins a comparatively small design, but keeping it in production costs almost nothing in node-transition spend. Longevity is not just a property of the product. It is the mechanism that makes the long-tail catalogue model viable at all.

Why analog stayed with the IDMs

Analog is one of the few IC segments where integrated device manufacturers, which both design and fabricate, have remained structurally competitive while logic shifted decisively to fabless. The book classifies analog and power-semiconductor IDMs as a medium-moat segment, sitting between the high-moat upstream layer (EDA, IP and lithography equipment) and the low-moat, scale-driven assembly layer. The margin framework the book uses, which flags several of its tier figures as needing evidence, gives the following picture.

Analog IDMs sit in the component-makers band: durable, but distinctly less extreme than the upstream layer. The book adds a caveat I think matters. The framework is a map of where value concentrates in principle, not a category-by-category prediction. A fabless logic company's economics behave more like the upstream IP tier than like this band, because its moat is design IP and not fabrication assets.

The foundries that opted out of the race

The persistence of analog on mature nodes is reinforced from an unexpected direction. Two of the top-five pure-play foundries have built their business around serving mature-node and specialty demand instead of chasing the leading edge. GlobalFoundries, spun off from AMD in 2009, deliberately focuses on RF, analog and embedded memory. UMC occupies a similar position among mature and specialty nodes. The book's Q1 2026 approximate shares, triangulated across sources and to be read as approximate, are:

UMC and GlobalFoundries together hold roughly 7% of global pure-play foundry revenue. That may look small beside TSMC's roughly 70%, but it is evidence that the mature-node profile of analog is large and durable enough to sustain dedicated foundry capacity that has consciously opted out of the node race. SMIC, at about 5.1%, is described in the book as a mature-node player expanding under export controls.

Where mixed-signal fits

Mixed-signal is the bridge, and it is not a niche. Almost every device that lets a digital system perceive or act on the physical world routes through a mixed-signal block. The book identifies three commercial families: power management ICs (an analog conversion stage plus a digital control loop), interface PHYs for PCIe, DDR5, USB4 and 112G/224G Ethernet (analog circuits managing signal integrity and clock recovery at multi-gigabit rates), and sensor interface and codec ICs (the analog front end and converter behind every accelerometer, gyroscope or MEMS microphone).

Within converters the central trade-off is resolution against speed. Precision instrumentation prioritises resolution because temperature and pressure change slowly; an RF receiver or high-speed serial link gives up some resolution to keep up with the signal. The direction of travel is tighter integration through chiplets and standards such as UCIe, which let a design combine a digital logic die, an analog RF or power die and a mixed-signal interface die in one package, each on the process node best suited to it. In effect, packaging lets analog and logic each get what they want from a node without making the other pay.

The chokepoint every category shares

All three categories share one upstream dependency: electronic design automation software and the IP cores licensed on top of it. The book puts Synopsys at about 31% and Cadence at about 30% of the global EDA and IP market, with Siemens EDA at about 13%, for roughly 74% across the top three of a market estimated at $14 billion to $16 billion. Siemens' Calibre is the de facto sign-off standard for design-rule checking and layout-versus-schematic verification. So a meaningful share of the value that logic, analog and mixed-signal teams create is captured at that one software and IP layer, before the fab is involved.

India's position

The book locates India overwhelmingly on the design side of the fabless-foundry split. Multinational semiconductor and EDA companies run substantial engineering operations in India that feed global design pipelines. A verified figure for the size of India's chip-design workforce, or its share of global IC design output by category, was not available in the reviewed sources, so I will not assert one. The India Semiconductor Mission, the Production-Linked Incentive scheme and SPECS are the three central vehicles aimed at broadening that presence. It is worth noting that analog's craft-heavy, talent-driven character is arguably a natural fit for a design-strong ecosystem, but that is my inference, not a sourced claim.

A worked contrast: a voltage reference against an SoC

To make the difference concrete, take two chips that might sit on the same board. One is a smartphone application SoC. The other is a precision voltage reference.

The SoC is the product of a leading-edge node. Its design team is betting that the phone will ship in volumes large enough to make the node's mask and verification costs a rounding error per unit. It mixes blocks with different priorities: fast execution cores, low-leakage SRAM, radio and image blocks. Samsung's continuously adjustable nanosheet width exists precisely to tune such blocks on one die. In two years a denser, faster competitor will make the design obsolete, and the vendor will be preparing its successor.

The voltage reference has no such clock. Its value is the stability and accuracy of one number. A newer node does not make it more stable, and nothing forces a redesign. If it meets its noise and accuracy specification, it remains the right part for a long time. The book's margin quote puts it well: the logic processor can be functionally obsolete within two years of tape-out, while the reference can be correct a decade later, which is why the categories are financed, staffed and valued differently.

The mixed-signal case that ties it together

The book's example of a mixed-signal design problem is the custom power management IC in the Apple Watch S-Series System-in-Package. It takes a noisy, variable input from a lithium-ion cell and a wireless-charging coil and delivers several clean, tightly regulated rails to a digital SoC, a display driver and an RF transceiver at once. That is a compact statement of everything in this article: a digital control loop wrapped around analog conversion, in a footprint with no room for discrete regulator stages. It is not a logic problem, because the hard part is the analog behaviour, and it is not a pure analog problem, because the sequencing and telemetry are digital. It shows why mixed-signal design sits where much of the system's value resides.

The foundry map behind all this

The foundry layer is worth a short note because it explains the fabless-versus-IDM divide. TSMC, at roughly 70% of pure-play foundry revenue in the book's Q1 2026 estimates, reported revenue of $40.2 billion for Q2 2026 and announced a further $100 billion Arizona investment, bringing its total committed US investment to $265 billion. Samsung Foundry targets 2nm-class volume production in 2026. Intel Foundry's 18A process combines gate-all-around transistors with backside power delivery, but Intel's own view is that yields will not reach world-class levels until 2027, and it has not yet secured external customers at scale.

All of that describes the leading-edge race, and it is the race analog largely sits out. That is the point. The most heavily capitalised part of the industry is built for a scaling logic that analog does not follow. The mature-node foundries, and the analog IDMs with their own fabs, serve the part of demand where the economics reward endurance over density.

How I would use this framing

For anyone analysing an IC company, the useful first question is which category it is really in. The framework in the book suggests a few readings.

• A company whose value comes from design IP behaves more like the upstream tier, whatever its product type.
• An analog IDM's durability comes from long product lives and a wide catalogue, not from riding a node curve.
• A fabless logic company's risk is concentrated in foundry access and volume, because it pays for node transitions whether or not a generation sells.
• Any of them shares exposure to the EDA and IP chokepoint, where Synopsys, Cadence and Siemens EDA hold roughly 74%.

The book is explicit that its margin framework is a map, not a prediction, and several tier-specific figures are flagged as requiring evidence. I keep the same caution here. The purpose is to give a sense of where value tends to sit, not to assign a number to a specific company.

What to take away

Logic follows the node: Samsung's 3nm gate-all-around node cut power by 45%, raised speed by 23% and shrank die area by 16% against 5nm FinFET, and only high-volume products can pay for that.

Analog does not, because matching, noise and parasitic capacitance are not solved by shrinking. That keeps the design flow manual, the parts on mature nodes, the product lives long and the catalogue wide, and it is why analog stayed IDM-heavy.

Mixed-signal bridges the two, with PMICs, converters and PHYs, and chiplet packaging is the mechanism that lets each function use its preferred node. The shared chokepoint is EDA and IP, where three firms hold roughly 74%. For India, the strength is on the design side, and the quantified scale is still an open evidence gap.