The Material Nobody Talks About

Between an advanced logic die and the printed circuit board it ends up on sits a few square centimetres of organic film that almost nobody outside packaging can name. It is called Ajinomoto Build-up Film, or ABF, and by the numbers in my source material, one company in Japan supplies roughly 99% to 100% of it. Every server CPU, GPU and AI accelerator that ships depends on it. I want to walk through what the material is, how it gets turned into wiring, who makes the finished substrates, and why the concentration matters more than its low public profile suggests.

One caution before I start. The book behind this article is explicit about where its evidence is thin, and I will keep those hedges. The ~99% to 100% share figure, for example, comes from Ajinomoto's own data, repeated across three overlapping references. It is one well-attested number, not three independent measurements. I will flag it each time it carries weight.

What a package substrate actually does

A package substrate is the organic interposer that bridges two interconnect worlds working at very different scales. On the die side, flip-chip micro-bump pitches are below 25 micrometres. On the board side, ball grid array pitches run from 0.5 to 1.0 millimetres. The substrate absorbs that fan-out, roughly twenty to forty times, through successive build-up layers of fine copper routing separated by an organic dielectric. It is the same architecture as a printed circuit board in miniature, built to tolerances an order of magnitude tighter.

Two material families supply that dielectric, and which one a package uses depends mostly on what kind of die it carries.

ABF is a thermosetting epoxy film, invented by Ajinomoto Fine-Techno, filled with spherical silica nano-fillers at loadings reported up to 70% by weight. It is the dielectric for flip-chip BGA (FC-BGA) packages: high-performance CPUs, GPUs and AI accelerators. Reported properties include insulation resistance above 10¹⁴ ohm-centimetres, a dissipation factor around 0.003 at 10 GHz, uniform laser-drillability and a comparatively low coefficient of thermal expansion (CTE).

BT resin is bismaleimide-triazine, developed by Mitsubishi Gas Chemical. It serves flip-chip chip-scale packages (FC-CSP), wire-bond packages, system-in-package modules and memory substrates such as eMMC, UFS and LPDDR5X. Its advantages are a high glass transition temperature, mechanical rigidity and strong resistance to migration under humidity and bias. Those suit smaller, lower-layer-count mobile and memory substrates, not the largest compute packages.

The book notes a small internal discrepancy: the ABF CTE upper bound is 12.0 ppm/°C in the table source but about 10.0 in a companion passage. I have kept the wider range rather than pick one. It also notes that these bands are compiled technical benchmarks, not figures from a single vendor datasheet.

The last row of that table is the one that decides how the materials are used. FR-4, processed subtractively, cannot resolve traces finer than about 50 micrometres. That is fine for a circuit board and hopeless for the die-to-substrate fan-out region. ABF and BT close the gap by pairing a laser-drillable dielectric with an additive process that resolves traces roughly ten to twenty-five times finer. So the largest and most transistor-dense dies, which have the highest per-package cost tolerance and the most routing complexity, go on ABF FC-BGA stacks reported at 10 to 24 build-up layers. Cost-sensitive, high-volume mobile and memory packages go on BT FC-CSP at 2 to 8 layers. The book does not quantify the cost gap between the two constructions, only the layer counts and geometries that drive it.

Why additive processes beat etching

An ordinary board is built subtractively. A full copper sheet, typically 18 or 35 micrometres thick, is laminated to the dielectric, a photoresist defines the pattern, and everything unwanted is etched away. The trouble is that the etchant also creeps sideways under the edge of the mask. That undercut gives the trace a trapezoidal cross-section and sets the practical floor of roughly 50 micrometres line and space.

Package substrates use one of two additive sequences, both of which start from very little copper and plate the pattern up only where it is wanted.

Two more caveats from the book. The mSAP minimum is 12 micrometres in two source documents and 15 for BT FC-CSP in a third. The SAP via diameter is reported as 10 to 20, 15 to 25 and 10 to 35 micrometres in different places, and the widest span is shown above. Read both as approximate, not as verified specifications.

The modified semi-additive process (mSAP) starts from a thin copper foil of 2 to 3 micrometres laminated to the core. Vias are laser-drilled, an electroless copper seed goes over the panel, copper is plated into the pattern through a dry-film resist, and a differential flash etch strips only the thin original foil from the uncovered areas. That etch is short, so undercut is small. The full semi-additive process (SAP) skips foil entirely. It starts from the bare, laser-drilled dielectric, deposits an electroless copper seed 0.3 to 0.8 micrometres thick, plates the pattern through resist, strips the resist and flash-etches only the residual seed. With no foil, there is nothing to undercut, and that is what makes 2 micrometre line and space reachable.

Laser drilling

Blind microvias link adjacent copper layers through the dielectric, and two lasers cut them. CO2 lasers, at roughly 9.4 to 10.6 micrometres wavelength, are absorbed strongly by organic resin. They drill larger vias, reported at 50 to 100 micrometres, at high throughput, cited above 3,000 vias per second. Ultraviolet third-harmonic Nd:YAG lasers at 355 nanometres work differently. Their photon energy breaks chemical bonds in the resin directly, which is photolytic ablation, not simple heating. That lets them cut the finer vias, roughly 10 to 35 micrometres, that SAP-class ABF substrates need, through resin and thin copper alike.

Desmear

Drilling leaves a mess. Local heating, reported above 300°C, melts a thin layer of epoxy that smears across the copper pad at the via bottom. Left in place, it causes open circuits once plating starts. A three-step wet chemistry removes it. A glycol ether sweller opens micro-pores in the epoxy. An alkaline potassium permanganate bath etches away the smear and leaves a honeycomb-textured surface, reported at a roughness (Rz) of about 0.2 to 0.5 micrometres, which gives copper something to key into. A hydrogen peroxide and sulfuric acid neutraliser then reduces the manganese dioxide residue to soluble manganese ions.

Electroless copper follows in two stages. A palladium and tin chloride colloidal catalyst deposits sub-nanometre palladium seeds in those micro-pores. The seeds then catalyse an autocatalytic reaction in which formaldehyde reduces dissolved copper sulfate to metallic copper. It needs no external current, which matters because the surface is not yet conductive. Only after that seed exists can electrolytic plating build the trace, selectively, through the resist. The book notes that these reaction sequences are reproduced as presented in the source material, without a dated laboratory citation for the equations themselves.

The chokepoint beneath every FC-BGA package

Now the fact that makes ABF strategically different from BT or any other packaging dielectric. Ajinomoto Fine-Techno's share of global ABF film supply is reported at roughly 99% to 100% in every source the book consulted, and every one of them calls it a monopoly. As I said at the top, that is one figure sourced to Ajinomoto's own data and repeated, not independently audited. The book also finds no regional breakdown, no segment breakdown and no time series.

The dependency is deeper than a supplier statistic, because it is embedded in the process. Every FC-BGA substrate maker laminates the same film from the same supplier before it drills a single via. SAP is not merely compatible with ABF. The process sequence, the desmear chemistry and the fine-pitch geometries the industry standardised around were all developed around ABF's laser-drillability, its dielectric profile and its CTE. A fabricator cannot swap in another film without requalifying an entire line. That is the sense in which the book compares this chokepoint to ASML's EUV lithography monopoly or KLA's dominance in wafer inspection: capability concentrated not because competitors are barred, but because know-how, qualification cycles and switching costs make displacing the incumbent unattractive.

There is a second difference from the equipment examples, and I think it is the more important one. This is a materials chokepoint, not a capital-equipment one. It does not need an export licence on a scanner costing hundreds of millions to constrain global capacity. It only needs continuity of chemical supply from a single manufacturing base. The book argues this makes it less visible in policy discussion and, in a disruption, potentially faster-acting, since substrate makers typically hold thinner safety stocks of a specialty film than fabs hold of equipment spares. It is careful to say that no source quantifies ABF safety-stock levels or the time-to-impact of a hypothetical supply disruption. I would treat that as a reasoned hypothesis, not a measured fact.

The scale of attention is also lopsided. Public discussion of semiconductor concentration gravitates to EUV lithography, leading-edge foundries and HBM memory. ABF sits one step downstream of all that, on a substrate most non-specialists have never heard of, made by a company best known publicly as a Japanese food and seasoning manufacturer. A fab needs a handful of lithography tools. A substrate maker needs ABF continuously, shipment after shipment, for the life of every product line.

Who turns the film into a package

Downstream of the film, the firms that laminate, drill, desmear and plate it sit in a less concentrated but still narrow layer. The book names seven.

What the book cannot give me is a ranking. There are no revenue, capacity or market-share figures for any of these firms in its sources, and no split of who specialises in ABF versus BT. If you want to know which of them leads in FC-BGA capacity or which serves which OEM, that answer is not here, and I would rather say so than guess. What I can say is structural. A 24-layer ABF stack at 2 micrometre line and space needs a different, larger investment in equipment, cleanroom discipline and process control than an 8-layer BT stack at 12 to 15 micrometres. That plausibly explains why the same firms do not compete evenly in both segments.

The geography is a familiar one. Japan, Taiwan and South Korea also dominate front-end wafer fabrication and OSAT packaging elsewhere in the book. That is consistent with the usual pattern of vertical clustering, where nearness to assembly houses, board makers and upstream material suppliers cuts logistics friction and qualification time, although the sources do not independently establish it.

The warpage problem that motivates glass

Every organic substrate shares one physical limit. Silicon has a low CTE, reported at about 2.6 ppm/°C. ABF and BT expand at roughly 10 to 15 ppm/°C, three to six times faster. During reflow, at around 260°C, that mismatch drives warpage, a convex or concave bend across the package that can crack solder joints or delaminate layers.

Substrate makers manage this today with three mitigations. Symmetric stackups mirror copper and dielectric thickness across the core so expansion forces balance. Low-CTE cores, such as Invar metal or high-modulus glass-reinforced cores, narrow the gap. Corner dummy copper pours equalise stress across the panel. These work within the limits of an organic dielectric but do not remove the mismatch, and the book says they become hard to sustain for AI chiplet packages larger than about 100 millimetres by 100 millimetres.

Intel, Samsung and Absolics are reported to be developing glass-core substrates in response. Glass is claimed to offer surface roughness below 0.5 nanometres, a CTE that can be tuned to about 3.0 ppm/°C to match silicon directly, and thermal stability that eliminates sag at 260°C reflow. The book is direct that these claims come from one of its three source documents, uncorroborated by the other two. It reports no shipping timeline, named product, yield or cost comparison, and it does not say how SAP-class lithography and desmear chemistry, all built around organic film, would change for glass. I take up that question in the companion article on glass-core substrates.

What to take away

First, ABF and BT are two different bets. ABF is for the biggest, densest dies at up to 24 layers and 2 micrometre geometries. BT is for volume mobile and memory at 2 to 8 layers and 12 to 15 micrometres.

Second, the additive process is the real enabler. The film matters because a whole lithography and chemistry sequence was built around it, which is also why the switching cost is so high.

Third, the ~99% to 100% share is a single-sourced figure, but consistent, and it describes a materials chokepoint that gets far less attention than lithography. The disruption-speed argument is reasoned, not measured.

Fourth, there is a genuine data gap. I cannot rank the seven named substrate makers, and I cannot size the ABF market in dollars from this book. Anyone who quotes you those numbers with confidence is working from sources I have not seen.

Finally, the CTE mismatch is the reason the industry is looking past organic film at all. That is where the next article picks up.