Neuromorphic computing, two-dimensional materials, and quantum computing hardware are routinely grouped as the beyond-CMOS frontier. They are three unrelated research programmes united mostly by one shared move: each questions an assumption that the rest of the electronics industry treats as settled, namely that computation happens in silicon transistors switching binary states at ever-higher density.
The closing chapter of my ESDM book is about these three, and it is the thinnest-sourced chapter in the whole volume. I found no dedicated primary research on any of them in the repository behind the book, one narrow data point excepted. I think that is worth turning into an article, because it raises a useful question. How should an analyst write about a technology whose physics is established but whose manufacturing economics cannot yet be measured? This piece tries to answer that, and to give readers a way to judge claims made in this phase.
Why these three are grouped, and why they should not be
What justifies discussing them together is a shared long-horizon question: what happens to electronics manufacturing when conventional transistor scaling, the Moore's Law and Wright's Law logic that has driven the industry since 1947, reaches its practical limits. All three are commonly cited as candidate answers.
What argues against grouping them is almost everything else. They come from different corners of physics and computer engineering, have different research histories, and sit at different distances from production. None is a near-term production category comparable to wide-bandgap power devices. All three remain substantially in the research, pilot-line, or early-commercialisation stage. Treating them as one market, or one bet, would be a category error, and much of the poorer commentary on this area makes it.
Neuromorphic computing
Conventional processors follow the von Neumann pattern. A processor repeatedly fetches instructions and data from a physically separate memory. The public research literature is consistent that a large share of the energy budget goes into moving data between compute and memory rather than computing on it. Neuromorphic architectures aim to reduce that cost for specific workloads by co-locating memory and computation, or by processing information as sparse, asynchronous spikes modelled loosely on biological neurons instead of as continuously clocked binary operations.
The workloads usually named are pattern recognition, sensor fusion, and always-on edge inference. Research-scale demonstrations are a matter of public record: IBM's TrueNorth chip from 2014 and Intel's Loihi research processors are among the best documented. I cite them as public facts, in the same register as Bell Labs' 1947 transistor. That existence says nothing about commercial maturity, shipping volume, or competitive standing, and I hold no research on any of those.
The one sourced data point
I did find one directly sourced fact. A file on radiation-hardened electronics, profiling suppliers of space-grade FPGAs and processors, notes in passing that Frontgrade Gaisler holds a Swedish National Space Agency contract to commercialise the GR801 "GRAIN" neuromorphic space system-on-chip. It was developed in the context of European sovereignty-focused semiconductor programmes, including the Horizon Europe COSMIC7 initiative.
That is a real and citable fact about one neuromorphic hardware programme in one narrow niche, radiation-tolerant space processors. It is not evidence of a broader neuromorphic market, and it says nothing about volume. I report it as exactly that. There is a reason space is a plausible early home for such a chip: power and mass budgets are tight and inference at the edge has value. But that reasoning is mine, not the source's, and I flag it as such.
Two-dimensional materials
Two-dimensional materials are crystals that can be isolated down to a single atomic layer, or a small stack of them, rather than existing only as a three-dimensional bulk solid. Graphene, a single layer of carbon atoms in a hexagonal lattice, was first isolated in 2004 by Andre Geim and Konstantin Novoselov, work recognised by the 2010 Nobel Prize in Physics. The wider family includes transition-metal dichalcogenides such as molybdenum disulphide, or MoS2, and tungsten diselenide, plus insulating layers such as hexagonal boron nitride.
The relevance to electronics manufacturing is direct. As transistor channel geometries shrink toward atomic dimensions, silicon's material properties get harder to control. A channel that is only a few atoms thick has a natural advantage in that regime, since its thickness is set by the crystal rather than by a process. That is why 2D semiconductors are researched as a possible successor channel material for logic beyond the gate-all-around nanosheet generation, alongside other post-silicon approaches I have not researched.
The careful statement is that this is a research direction under active investigation across academia and industry. It is not a claim that any specific manufacturer has committed to a 2D-channel production roadmap. My repository has no evidence either way. The hard problems, as I understand them from general literature, are the ones any new channel material meets: growing uniform layers over a full wafer, making low-resistance contacts, and integrating with existing processes. I list them as questions, not as findings.
| Frontier | Well-established public facts | What I cannot source |
|---|---|---|
| Neuromorphic | Memory-compute co-location; spiking architectures; TrueNorth (2014) and Loihi as research chips | Market size, shipping volumes, competitive standing |
| 2D materials | Graphene isolated in 2004; Nobel Prize 2010; MoS2 and related crystals researched as post-silicon channels | Any manufacturer's production roadmap; yield or cost data |
| Quantum hardware | Qubit modalities: superconducting, trapped ion, photonic, neutral atom, silicon spin | Which modality scales; manufacturable volumes; supplier landscape |
Quantum computing hardware
Quantum hardware is the physical engineering of qubits, the information-carrying elements of a quantum computer, whose behaviour uses superposition and entanglement rather than the definite 0-or-1 states of a classical transistor. Several physical implementations are pursued in parallel: superconducting circuits, trapped ions, photonic qubits, neutral atoms, and semiconductor spin qubits fabricated in silicon.
The link to electronics manufacturing is concrete even where the qubit itself is not built from silicon. Most approaches depend on cryogenic control electronics, specialised RF and microwave packaging, and ultra-low-noise interconnect. Those sit next to capabilities that advanced packaging and RF front-end manufacturing already provide in a conventional-computing context. That is the point at which ESDM, as an industry, is relevant to quantum hardware, and it is a supply chain observation rather than a market forecast.
Which modality will prove most manufacturable at scale is an open and actively contested question. A chapter or an article that names a winner is not drawing on primary quantum-hardware research, and I do not. I also want to correct a mistake I nearly inherited. An earlier draft of my chapter asserted that India's Tata Dholera and Micron Sanand facilities were producing silicon spin-qubit processors. They are not. Dholera is a planned 28nm wafer fab and Sanand is a memory packaging facility, and I have no evidence connecting either to quantum hardware. Any claim of that kind should be treated with suspicion until a source is produced.
When a draft on an emerging technology arrives with confident market benchmarks and a tidy local case study, the missing ingredient is usually the source. The right response to a gap in evidence is to mark it, not to fill it with plausible numbers.
What the investment data does and does not say
The place I checked last for a grounded connection was private equity and venture capital research, since neuromorphic accelerators, novel semiconductor materials, and quantum hardware startups are the kind of deep-tech ventures a VC-trends file might track. The file I hold names custom AI inference chips, RISC-V processor design houses, silicon photonics, and wide-bandgap power devices as its focus areas. It names none of the three frontiers here. Its headline global semiconductor VC funding figure is also marked unverified against the source it cited.
So I do not stretch a general "deep-tech investment is elevated" framing to cover these three fields. That extension would be exactly the unsupported inference an evidence standard exists to prevent. The honest summary is that my investment research is as silent on these frontiers as my technical research.
Why the manufacturing layer decides which frontier matters
There is a pattern in the industry's history that I find more useful than any forecast. A physical effect can be demonstrated in a laboratory long before anyone can make it repeatedly, cheaply, and at yield. The gap between those two is where most of the cost, time, and failure sits. It is also where supply chains get built: the equipment, the ultra-pure inputs, the process control, and the qualified suppliers that turn a demonstration into a product.
Each of the three frontiers has its own version of that gap, and I think it is more informative to describe the gap than to guess the outcome. For neuromorphic chips, the gap is largely about software and workloads: an architecture that saves energy on the right task is only valuable if enough customers have that task and can program the hardware. The fabrication itself can lean on existing silicon lines. For 2D materials the gap is materials engineering. A channel is only as good as the uniformity of the layer, the quality of the contacts, and the ability to integrate it into a flow that already runs at high volume. For quantum hardware the gap is control and scale: the qubit is one part of a system that also needs cryogenics, microwave control, and low-noise wiring, and each of those has to scale together.
What follows for the electronics manufacturing industry is a set of second-order questions that I can state without a forecast. Which existing capabilities, such as advanced packaging, RF and microwave assembly, ultra-pure materials, and wafer-scale epitaxy, will be asked to serve these programmes? Which of them are already concentrated in a few suppliers, as other chapters of the book show for many specialty inputs? And which national programmes are building the adjacent capability now, before any of the frontiers is proven? Those questions can be researched. I have not researched them for these three fields, and I would rather leave them open than answer them by analogy.
There is also a reporting habit to be aware of. Announcements of research milestones, such as a record number of qubits, a new transistor demonstrated in a single-layer crystal, or a chip that runs a benchmark at low power, are real results. They are also steps within the research phase, and they rarely come with the yield and cost data that would place them on a manufacturing curve. I read them as evidence that the science is progressing, and I keep them separate from evidence that an industry is forming. Conflating the two is how a sound physics headline turns into an unsupported market forecast.
Why the analogy to earlier waves is limited
It is tempting to say that because compound semiconductors and advanced packaging went from research to production, these will too. The earlier cases are useful as a pattern of phases, which is how I use them above. They are weak as predictions, because each frontier depends on a different, specific bottleneck, and survivorship makes the successful cases look inevitable in hindsight. Many research programmes with sound physics never reached volume, and the record of which ones did is a record of manufacturing and economics as much as of science.
Reading claims made in the pre-industrial phase
The book opens with a precisely dated event, the point-contact transistor at Bell Labs in December 1947, and traces a seventy-year pattern from it: a foundational discovery, a slow and uneven route to manufacturability, premium low-volume adoption before consumer-scale production, and then a compounding density-and-cost curve that reorganised an industry. Every earlier chapter is an account of some portion of that pattern already having played out, and where the research allowed, it could be quantified.
The three frontiers here are, in my reading, in the phase the transistor occupied between 1947 and the late 1950s. Real physical demonstrations exist. The community understands the science reasonably well. The open questions are overwhelmingly about manufacturability, yield, cost, and which of several competing approaches will scale, not about whether the physics works. That is exactly the phase when confident market-sizing and competitive-positioning claims are least reliable.
So here is how I would read anything written about them, including the more enthusiastic coverage. These are the tests I apply.
Ask what kind of statement it is
A statement about physics, such as a qubit's superposition or a monolayer's thickness, can be checked against the scientific literature. A statement about a demonstration, such as a research chip existing, is a matter of public record. A statement about a market, such as a size, a growth rate, or a share, needs a source with a method. The boundary between the second and third kinds is where most inflated claims cross over.
Ask for the manufacturing evidence
Yield, cost per unit, and volume are the evidence that separates a lab result from an industrial product. If they are absent, the honest description is a research programme. The absence is not a criticism. It is simply where the technology sits.
Ask whether a local story is documented
Claims that a specific factory or country is already building a frontier product deserve the highest scepticism. The correction I made about Dholera and Sanand is an example. Real facilities, real programmes, and no evidence of the claimed link.
Ask what is actually adjacent
The most defensible ESDM connections are in the surrounding electronics: cryogenic control electronics and microwave packaging for quantum, CMOS fabrication for neuromorphic, and wafer-scale growth and contact engineering for 2D materials. Those are existing capabilities meeting new demand, and they can be discussed without predicting which frontier wins.
What to take away
Neuromorphic computing, 2D materials, and quantum hardware are three well-established research fields that answer one shared question about the end of conventional scaling. They should not be analysed as one market.
My sources contain no primary research on any of them. The single sourced data point is Frontgrade Gaisler's GR801 GRAIN neuromorphic space processor under a Swedish National Space Agency contract: one programme, one niche, not a market.
The open questions are about manufacturability, yield, cost, and modality, not about physics. That is the phase where market-sizing claims deserve the most scepticism.
The book opens with an industry whose founding moment is exactly dated and thoroughly documented, and it closes with three research programmes whose industrial significance is genuinely unknown. Not unknown to physics, but unknown to the manufacturing economics, supply chains, and national strategies that make up the subject of my work. I think recording that plainly is more useful than manufacturing a false completeness. The task left for the next research pass is to build the primary base for these fields: supplier and programme documentation, verifiable manufacturing and yield data, and case studies checked against source. Until it exists, the best an analyst can do is say which statements are physics, which are demonstrations, and which are guesses.